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| 型號： | EP6101 |
| 廠商： | Altera Corporation |
| 英文描述： | Classic EPLD Family(典型EPLD系列器件) |
| 中文描述： | 經(jīng)典系列可編程邏輯器件（典型可編程邏輯器件系列器件） |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 227K |
| 代理商： | EP6101 |
Altera Corporation
979
AN 78: Understanding MAX 5000 & Classic Timing
For Classic devices,
Figure 6
shows part of a
7483
TTL macrofunction (a
4-bit full adder). The Report File gives the following equations for
s1
, the
least significant bit of the adder:
S1
_EQ002 = A1 & B1 & C0
# !A1 & B1 & !C0
# A1 & !B1 & !C0
# !A1 & !B1 & C0;
= LCELL(_EQ002);
Figure 6. Adder Logic Timing for Classic Architecture
The
s1
output is the output of the macrocell which contains the
combinatorial logic. The
_EQ002
represents the equation that logically
represents the synthesized implementation of
a1
,
b1
, and
c0
. Therefore,
the timing delay for
s1
in Classic devices is as follows:
t
IN
+ t
LAD
+ t
OD
Example 2: Second Bit of 7483 TTL Macrofunction
For complex logic that requires expanders (represented as
_X
<number>
in
Report Files), the expander array delay,
t
SEXP
, is added to the delay
element.
tLAD
t
OD
tIN
a1
c0
b1
s1
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