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參數(shù)資料
| 型號(hào)： | EP6101 |
| 廠商： | Altera Corporation |
| 英文描述： | Classic EPLD Family(典型EPLD系列器件) |
| 中文描述： | 經(jīng)典系列可編程邏輯器件（典型可編程邏輯器件系列器件） |
| 文件頁(yè)數(shù)： | 14/15頁(yè) |
| 文件大?。?/td> | 227K |
| 代理商： | EP6101 |
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982
Altera Corporation
AN 78: Understanding MAX 5000 & Classic Timing
Figure 8. Adder Equations Mapped to Classic Architecture
Example 3: First Bit of 7483 TTL Macrofunction in Low-Power
Mode (Classic Devices)
If a Classic device macrocell is set for low-power mode, you must add the
low-power adder delay to the total delay through that macrocell. Thus,
the
s1
delay in
Figure 6
is as follows:
t
IN
+ t
LPA
+ t
LAD
+ t
OD
Conclusion
The MAX 5000 and Classic device architectures have fixed internal timing
delays that are independent of routing. Therefore, you can determine the
worst-case timing delays for any design before programming a device.
Total delay paths can be expressed as the sums of internal timing delays.
Timing models illustrate the internal delay paths for devices and show
how these internal timing parameters affect each other. You can use the
MAX+PLUS II Timing Analyzer to automatically calculate delay paths, or
hand-calculate delay paths by adding the internal timing parameters for
an appropriate timing model. With the ability to predict worst-case timing
delays, you can be confident of a design’s in-system timing performance.
c0
a1
a2
b1
b2
LC017
LC018
tLAD
tOD
tIN
s2
tLAD
tFD
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