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參數(shù)資料
| 型號(hào)： | EP7209 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | Ultra-Low-Power Audio Decoder System-on-Chip |
| 中文描述： | 超低功耗音頻解碼器系統(tǒng)級(jí)芯片 |
| 文件頁(yè)數(shù)： | 37/128頁(yè) |
| 文件大?。?/td> | 1382K |
| 代理商： | EP7209 |
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EP7209
DS453PP2
37
Data is loaded into the transmit FIFO by writing to
the CODR register. At the beginning of a transmit
cycle, this data is loaded into a shift/load register.
Just prior to the byte being transferred out, PCM-
SYNC goes high for one PCMCLK cycle. Then the
data is shifted out serially to PCMOUT, MSB first,
(with the MSB valid at the same time PCMSYNC
is asserted). Data is shifted on the rising edge of the
PCMCLK output.
Receiving of data is performed by taking data in se-
rially through PCMIN, again MSB first, shifting it
through the shift/load register and loading the com-
plete byte into the receive FIFO. If there is no data
available in the transmit FIFO, then a zero will be
loaded into the shift/load register. Input data is
sampled on the falling edge of PCMCLK. Data is
read from the CODR register.
3.11.2
Digital Audio Interface
The DAI interface provides a high quality digital
audio connection to DAI compatible audio devices.
The DAI is a subset of I2S audio format that is sup-
ported by a number of manufacturers.
The DAI interface produces one 128-bit frame at
the audio sample frequency using a bit clock and
frame sync signal. Digital audio data is transferred,
full duplex, via separate transmit and receive data
lines. The bit clock frequency is either fixed at
9.216 MHz or set via an externally supplied MCLK
signal.
The DAI interface contains separate transmit and
receive FIFO
’
s. The transmit FIFO
’
s are 8 audio
samples deep and the receive FIFO
’
s are 12 audio
samples deep.
DAI ADC
DAI DAC
7209
SCLK
LRCK
SDOUT
MCLK
SDIN
SCLK
LRCK
SDATA
MCLK
SCLK
LRCK
SDATA
MCLK
CLOCK
GEN
Figure 7. DAI Interface
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