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參數(shù)資料
| 型號： | EP7209 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | Ultra-Low-Power Audio Decoder System-on-Chip |
| 中文描述： | 超低功耗音頻解碼器系統(tǒng)級芯片 |
| 文件頁數(shù)： | 54/128頁 |
| 文件大小： | 1382K |
| 代理商： | EP7209 |
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EP7209
54
DS453PP2
Table 26. EP7209 Internal Registers (Big Endian Mode)
NOTE:
5.1.1
The following Register Descriptions refer to Little Endian Mode Only
PADR Port A Data Register
ADDRESS: 0x8000.0000
Values written to this 8-bit read/write register will be output on Port A pins if the corresponding data
direction bits are set high (port output). Values read from this register reflect the external state of Port
A, not necessarily the value written to it. All bits are cleared by a system reset.
5.1.2
PBDR Port B Data Register
ADDRESS: 0x8000.0001
Values written to this 8-bit read/write register will be output on Port B pins if the corresponding data
direction bits are set high (port output). Values read from this register reflect the external state of Port
B, not necessarily the value written to it. All bits are cleared by a system reset.
5.1.3
PDDR Port D Data Register
ADDRESS: 0x8000.0003
Values written to this 8-bit read/write register will be output on Port D pins if the corresponding data
direction bits are set low (port output). Values read from this register reflect the external state of Port
D, not necessarily the value written to it. All bits are cleared by a system reset.
5.1.4
PADDR Port A Data Direction Register
ADDRESS: 0x8000.0040
Bits set in this 8-bit read/write register will select the corresponding pin in Port A to become an output,
clearing a bit sets the pin to input. All bits are cleared by a system reset.
5.1.5
PBDDR Port B Data Direction Register
ADDRESS: 0x8000.0041
Bits set in this 8-bit read/write register will select the corresponding pin in Port B to become an output,
clearing a bit sets the pin to input. All bits are cleared by a system reset.
Big Endian Mode
Name
Default
RD/WR
Size
Comments
0x8000.0003
PADR
0
RW
8
Port A Data Register
Port B Data Register
Reserved
Port D Data Register
Port A data Direction Register
Port B Data Direction Register
Reserved
Port D Data Direction Register
Port E Data Register
Port E Data Direction Register
0x8000.0002
PBDR
0
RW
8
0x8000.0001
—
—
8
0x8000.0000
PDDR
0
RW
8
0x8000.0043
PADDR
0
RW
8
0x8000.0042
PBDDR
0
RW
8
0x8000.0041
—
—
8
0x8000.0040
PDDDR
0
RW
8
0x0000.0080
PEDR
0
RW
3
0X8000.0000
PEDDR
0
RW
3
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