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| 型號(hào)： | EP7211 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| 中文描述： | 高性能超低功耗系統(tǒng)與LCD控制器芯片 |
| 文件頁(yè)數(shù)： | 101/166頁(yè) |
| 文件大小： | 2623K |
| 代理商： | EP7211 |
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
101
Register Descriptions
DS352PP3
JUL 2001
The previous table preserves compatibility with the previous devices, while allowing the previously
unused bit combinations to specify more variations of random and sequential wait states.
See the
AC Electrical Specification
section for more detail on bus timing.
The memory area decoded by CS6 is reserved for the on-chip SRAM, hence this does not require a
configuration field in MEMCFG2. It is automatically set up for 32-bit wide, no wait state accesses.
For the Boot ROM, it is automatically set up for 8-bit, no wait state accesses.
Chip selects
NCS4
and
NCS5
are used to select two CL-PS6700 PC CARD controller devices. These
have a multiplexed 16-bit wide address/data interface, and the configuration bytes in the MEMCFG2
register have no meaning when these interfaces are enabled.
5.4.3
DRFPR DRAM Refresh Period Register
ADDRESS: 0x8000.0200
The DRAM refresh period register is an 8-bit read/write register which enables refreshes and selects
the refresh period used by the DRAM controller for its periodic CAS before RAS refresh. The value
1
1
1
1
1
0
Bit
Description
6
SQAEN
: Sequential access enable. Setting this bit will enable sequential accesses that are on a quad
word boundary to take advantage of faster access times from devices that support page mode. The
sequential access will be faulted after four words, (to allow video refresh cycles to occur) even if the
access is part of a longer sequential access. In addition, when this bit is not set, non-sequential accesses
will have a single idle cycle inserted at least every four cycles so that the chip select is de-asserted period-
ically between accesses for easier debug.
7
CLKENB
: Expansion clock enable. Setting this bit enables the
EXPCLK
to be active during accesses to
the selected expansion device. This will provide a timing reference for devices that need to extend bus
cycles using the
EXPRDY
input. Back to back (but not necessarily page mode) accesses will result in a
continuous clock. This bit will only affect
EXPCLK
when the PLL is being used (i.e., in 73.728
–
18.432MHz
mode). When operating in 13 MHz mode, the
EXPCLK
pin is an input so cannot be affected by this regis-
ter bit. To save power internally, it should always be set to zero when operating in 13 MHz mode.
7
6:0
RFSHEN
RFDIV
Table 5-6. Values of the Wait State Field at 36 MHz
(cont.)
Bit 3
Bit 2
Bit 1
Bit 0
Wait States
Random
Wait States
Sequential
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EP7211-CP-A | HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| EP7211-CV-A | HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| EP7212 | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
| EP7212-CB-A | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
| EP7212-CV-A | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP7211(208LQFP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| EP7211(256PBGA) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| EP7211-CB-D | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EP7211-CP-A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| EP7211-CV-A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
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