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| 型號(hào)： | EP7211 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| 中文描述： | 高性能超低功耗系統(tǒng)與LCD控制器芯片 |
| 文件頁(yè)數(shù)： | 111/166頁(yè) |
| 文件大?。?/td> | 2623K |
| 代理商： | EP7211 |
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
111
Register Descriptions
DS352PP3
JUL 2001
The length of the data frame can be programmed by writing to the SYNCIO register. This allows
many different ADCs to be accommodated. The device is SPI/Microwire compatible (transfers are
in multiples of 8 bits). However, to be compatible with some non-SPI/Microwire devices, the data
written to the ADC device can be anything between 8 to 16 bits. This is user-definable as defined in
the ADC Configuration Extension section of the SYNCIO register.
In the default mode, the bits in SYNCIO have the following meaning:
Whereas in extended mode, the following applies:
NOTE:
The frame length in extended mode is 6 bits wide to allow up to 16 write bits, 1 null bit and 16 read
bits (= 33 cycles).
31:15
14
13
12:8
7:0
Reserved
TXFRMEN
SMCKEN
Frame length
ADC Configuration Byte
15
14
13
12:7
6:0
Reserved
TXFRMEN
SMCKEN
Frame length
ADC Configuration
Length
31
16
ADC Configuration Extension
Bit
Description
0:7 or 0:6
ADC Configuration Byte
: When the ADCCON control bit in the SYSCON3 register = 0, this is the 8-bit
configuration data to be sent to the ADC. When the ADCCON control bit in the SYSCON3 register = 1, this
field determines the length of the ADC configuration data held in the
ADC Configuration Extension
field
for sending to the ADC.
8:12 or 7:12
Frame length
: The Frame Length Field is the total number of shift clocks required to complete a data
transfer.
In default mode, MAX148/9 (and for many ADCs), this is 25 = (8 for configuration byte + 1 null bit + 16 bits
result).
In extended mode, AD7811/12, this is 23 = (10 for configuration byte + 3 null + 10 bits result).
13
SMCKEN
: Setting this bit will enable a free running sample clock at twice the programmed ADC clock fre-
quency to be output on the
SMPLCK
pin.
14
TXFRMEN
: Setting this bit will cause an ADC data transfer to be initiated. The value in the ADC configura-
tion field will be shifted out to the ADC and depending on the frame length programmed, a number of bits
will be captured from the ADC. If the SYNCIO register is written to with the TXFRMEN bit low, no ADC
transfer will take place, but the Frame length and SMCKEN bits will be affected.
16:31
ADC Configuration Extension
: When the ADCCON control bit in the SYSCON3 register = 0 this field is
ignored for compatibility with the CL-PS7111. When the ADCCON control bit in the SYSCON3 register = 1,
this field is the configuration data to be sent to the ADC. The ADC Configuration Extension field length is
determined by the value held in the ADC Configuration Length field (SYNCIO[6:0]).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EP7211-CP-A | HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| EP7211-CV-A | HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| EP7212 | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
| EP7212-CB-A | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
| EP7212-CV-A | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP7211(208LQFP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| EP7211(256PBGA) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| EP7211-CB-D | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EP7211-CP-A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| EP7211-CV-A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
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