參數(shù)資料
型號： EP7211
廠商： Cirrus Logic, Inc.
英文描述： HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
中文描述： 高性能超低功耗系統(tǒng)與LCD控制器芯片
文件頁數(shù)： 122/166頁
文件大?。?/td> 2623K
代理商： EP7211
EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
122
Register Descriptions
DS352PP3
JUL 2001
5.16.2.2
MCP Data Register 1
ADDRESS: 0x8000.2080
When MPC Data Register 1 (MCDR1) is read, the bottom entry of the telecom receive FIFO is
accessed. As data is removed by the MCP
’
s receive logic from the incoming data frame, it is placed
into the top entry of the telecom receive FIFO and is transferred down an entry at a time until it
reaches the last empty location within the FIFO. Data is removed by reading MCDR1, which
accesses the bottom entry of the telecom FIFO. After MCDR1 is read, the bottom entry is
invalidated, and all remaining values within the FIFO automatically transfer down one location.
When MCDR1 is written, the top-most entry of the telecom transmit FIFO is accessed. After a write,
data is automatically transferred down to the lowest location within the transmit FIFO which does
not already contain valid data. Data is removed from the bottom of the FIFO one value at a time by
the transmit logic. It is then loaded into the correct position within the 64-bit transmit serial shifter
then serially shifted out onto the
SIBDOUT
pin during subframe 0.
Telecom data is 14-bits wide and must be left justified by the user before writing them to the transmit
FIFO (MSB of telecom data corresponds to bit 16 of transmit FIFO). The lower two bits of the FIFO
which are aligned within the 16-bit value are also written to MCDR1 for transmission. The UCB1100
automatically forces bits 0 and 1 to zero before transmitting the value to the MCP. The user must
right justify received telecom data before using it.
Table 5-14. MCP Data Register 0
Bit
Name
Description
3
–
0
—
Reserved for future enhancements
Read
—
Data returned, but UCB1100 currently zero fills these four bits
Write
—
MCP
’
s transmit logic sends these bits, even though they are ignored by the UCB1100
15
–
4
Audio
Data
Transmit/Receive Audio FIFO Data
Read
—
Bottom of Audio Receive FIFO data
Write
—
Top of Audio Transmit FIFO data
31
–
16
—
Reserved
相關(guān)PDF資料
PDF描述
EP7211-CP-A HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
EP7211-CV-A HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER
EP7212 HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CB-A HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CV-A HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
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