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| 型號： | EP7211 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| 中文描述： | 高性能超低功耗系統(tǒng)與LCD控制器芯片 |
| 文件頁數(shù)： | 40/166頁 |
| 文件大?。?/td> | 2623K |
| 代理商： | EP7211 |
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
40
Functional Description
DS352PP3
JUL 2001
Table 3-4
summarizes the three external interrupt sources and the effect they have on interrupt pins.
For the case of the keyboard interrupt, the following options are available and are selectable
according to bits 1 and 3 of the SYSCON2 register (refer to SYSCON2 register description for
details).
If the KBWEN bit (SYSCON2 Bit 3) is set low, then a keypress will cause a transition from a
power saving state only if the keyboard interrupt is non-masked (i.e., the interrupt mask register
2 (INTMR2 bit 0) is high).
When KBWEN is high, a keypress will cause the device to wake up regardless of the state of the
interrupt mask register. This is called the
“
Keyboard Direct Wakeup
’
mode. In this mode, the
interrupt request may not get serviced. If the interrupt is masked (i.e., the interrupt mask register
2 (INTMR2 bit 0) is low), the processor simply starts re-executing code from where it left off
before it entered the power saving state. If the interrupt is non-masked, then the processor will
service the interrupt.
When the KBD6 bit (SYSCON2 Bit 1) is low, all 8 of Port A inputs are OR
’
ed together to
produce the internal wakeup signal and keyboard interrupt request.
This is the default reset
state.
When the KBD6 bit (SYSCON2 Bit 1) is high, only the lowest 6 bits of Port A are OR
’
ed
together to produce the internal wakeup signal and keyboard interrupt request. The two most
significant bits of Port A are available as GPIO when this bit is set high.
Table 3-4. External Interrupt Source Latencies
Interrupt
Pin
Input State
Operating
State
Latency
Idle State
Latency
Standby State Latency
NEXTFIQ
Not deglitched;
must be active for
20
μ
s to be
detected
Worst case
latency of 20
μ
s
Worst case 20
μ
s: if only sin-
gle cycle
instructions,
less than
1
μ
s
Including PLL/osc. settling time,
approx. 0.25 s when FASTWAKE
= 0, or approx. 500 μs when
FASTWAKE = 1, or = Idle State if
in 13 MHz mode with CLENSL set
NEINT1
–
2
Not deglitched
Worst case
latency of 20
μ
s
As above
As above
EINT3
Not deglitched
Worst case
latency of 20
μ
s
As above
As above
MEDCHG
Deglitched by
16 kHz clock; must
be active for at
least 80
μ
s to be
detected
Worst case
latency of 80
μ
s
Worst case 80
μ
s: if only sin-
gle cycle
instructions,
61
μ
s
As above (note difference if in 13
MHz mode with CLKENSL set)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EP7211-CP-A | HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| EP7211-CV-A | HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| EP7212 | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
| EP7212-CB-A | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
| EP7212-CV-A | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP7211(208LQFP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| EP7211(256PBGA) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| EP7211-CB-D | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EP7211-CP-A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| EP7211-CV-A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
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