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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
6
DS352PP3
JUL 2001
3.11.2
Prescale Mode ...........................................................................................................................68
3.12 Realtime Clock........................................................................................................................................68
3.13 Dedicated LED Flasher...........................................................................................................................68
3.14 Two PWM Interfaces...............................................................................................................................69
3.15 State Control............................................................................................................................................69
3.16 Resets.....................................................................................................................................................72
3.17 Clocks......................................................................................................................................................73
3.17.1 On-Chip PLL...............................................................................................................................73
3.17.2 External Clock Input (13 MHz) ...................................................................................................74
3.18 Dynamic Clock Switching When in the PLL Clocking Mode....................................................................75
3.19 Endianness..............................................................................................................................................75
3.20 Maximum EP7211-Based System...........................................................................................................77
3.21 Boundary Scan........................................................................................................................................78
3.22 In-Circuit Emulation.................................................................................................................................79
3.22.1 Introduction.................................................................................................................................79
3.22.2 Functionality...............................................................................................................................79
4. MEMORY MAP.........................................................................................................................80
5. REGISTER DESCRIPTIONS ...................................................................................................81
5.1
Internal Registers....................................................................................................................................81
5.1.1
PADR Port A Data Register........................................................................................................85
5.1.2
PBDR Port B Data Register .......................................................................................................85
5.1.3
PDDR Port D Data Register.......................................................................................................85
5.1.4
PADDR Port A Data Direction Register......................................................................................85
5.1.5
PBDDR Port B Data Direction Register......................................................................................85
5.1.6
PDDDR Port D Data Direction Register .....................................................................................85
5.1.7
PEDR Port E Data Register .......................................................................................................86
5.1.8
PEDDR Port E Data Direction Register......................................................................................86
5.2
SYSTEM Control Registers.....................................................................................................................86
5.2.1
SYSCON1 The System Control Register 1................................................................................86
5.2.2
SYSCON2 System Control Register 2 .......................................................................................89
5.2.3
SYSCON3 System Control Register 3 .......................................................................................91
5.2.4
SYSFLG
—
The System Status Flags Register .........................................................................92
5.2.5
SYSFLG2 System Status Register 2..........................................................................................94
5.3
Interrupt Registers...................................................................................................................................95
5.3.1
INTSR1 Interrupt Status Register 1............................................................................................95
5.3.2
INTMR1 Interrupt Mask Register 1.............................................................................................97
5.3.3
INTSR2 Interrupt Status Register 2............................................................................................97
5.3.4
INTMR2 Interrupt Mask Register 2.............................................................................................98
5.3.5
INTSR3 Interrupt Status Register 3............................................................................................98
5.3.6
INTMR3 Interrupt Mask Register 3.............................................................................................99
5.4
Memory Configuration Registers.............................................................................................................99
5.4.1
MEMCFG1 Memory Configuration Register 1............................................................................99
5.4.2
MEMCFG2 Memory Configuration Register 2..........................................................................100
5.4.3
DRFPR DRAM Refresh Period Register..................................................................................102
5.5
Timer/Counter Registers .......................................................................................................................103
5.5.1
TC1D Timer Counter 1 Data Register ......................................................................................103
5.5.2
TC2D Timer Counter 2 Data Register ......................................................................................103
5.5.3
RTCDR Realtime Clock Data Register.....................................................................................103
5.5.4
RTCMR Realtime Clock Match Register..................................................................................103