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參數(shù)資料
| 型號(hào)： | EP7211 |
| 廠商： | Cirrus Logic, Inc. |
| 英文描述： | HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| 中文描述： | 高性能超低功耗系統(tǒng)與LCD控制器芯片 |
| 文件頁數(shù)： | 90/166頁 |
| 文件大?。?/td> | 2623K |
| 代理商： | EP7211 |
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EP7211
High-Performance Ultra-Low-Power System-on-Chip with LCD Controller
90
Register Descriptions
DS352PP3
JUL 2001
5.2.3
SYSCON3 System Control Register 3
ADDRESS: 0x8000.2200
This register is an extension of SYSCON1 and SYSCON2, containing additional control for the
EP7211. The bits of this third system control register are defined below.
15
14
13
12
11
10
9
8
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
FASTWAKE
7
6
5
4
3
2
1
0
VERSN[2]R
eserved
VERSN[1]
Reserved
VERSN[0]
Reserved
ADCCKNSEN
MCPSEL
CLKCTL1
CLKCTL0
ADCCON
Bit
Description
8
FASTWAKE
: When set, the device will wake from the Standby State within one to two cycles of a 4 kHz
clock. This bit is cleared at power up, and thus the device first starts using the default one to two cycles of
the 8 Hz clock.
5:7
VERSN[2:0]
: Additional read-only version bits
—
will read
‘
000
’
.
4
ADCCKNSEN
: When set, configuration data is transmitted on
ADCOUT
at the rising edge of the
ADC-
CLK,
and data is read back on the falling edge on the
ADCIN
pin. When clear (default), the opposite
edges are used.
3
MCPSEL
: When set selects the MCP. This defaults to either the SSI or codec (i.e., MCPSEL bit is low).
0
ADCCON
: Determines whether the ADC Configuration Extension field SYNCIO(31:16) is to be used for
ADC configuration data. When this bit = 0 (default state) the ADC Configuration Byte SYNCIO(7:0) only is
used for compatibility with the CL-PS7111. When this bit = 1, the ADC Configuration Extension field in the
SYNCIO register is used for ADC Configuration data and the value in the ADC Configuration Byte (SYN-
CIO(6:0)) selects the length of the data (8-bit to 16-bit).
1:2
CLKCTL(1:0)
: Determines the frequency of operation of the processor and Wait State scaling. The table
below lists the available options.
NOTE: To determine the number of wait states programmed refer to
Table 5-4. Values of the Wait State
Field at 13 and 18MHz
and
Table 5-5. Values of the Wait State Field at 36 MHz
. When operating at 13
MHz, the CLKCTL[1:0] bits should not be changed from the default value of
‘
00
’
. Under no circumstances
should the CLKCTL bits be changed using a buffered write.
CLKCTL(1:0)
Value
Processor
Frequency
ASB and APB
Frequency
Wait State
Scaling
00
18.432 MHz
18.432 MHz
1
01
36.864 MHz
36.864 MHz
2
10
49.152 MHz
36.864 MHz
2
11
73.728 MHz
36.864 MHz
2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EP7211-CP-A | HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| EP7211-CV-A | HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| EP7212 | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
| EP7212-CB-A | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
| EP7212-CV-A | HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP7211(208LQFP) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| EP7211(256PBGA) | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Logic IC |
| EP7211-CB-D | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EP7211-CP-A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
| EP7211-CV-A | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE ULTRA-LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER |
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