參數(shù)資料
型號(hào)： EP7212
廠商： Cirrus Logic, Inc.
英文描述： HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
中文描述： 高性能，低功耗系統(tǒng)與LCD控制器和數(shù)字音頻接口（DAI芯片）
文件頁(yè)數(shù)： 50/136頁(yè)
文件大小： 2289K
代理商： EP7212
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EP7212
50
DS474PP1
low) is determined by latching the state of this
drive signal during power on reset (i.e., a pull-up on
the drive signal will result in a active low drive out-
put, and visa versa). This allows either positive or
negative voltages to be generated by the external
DC-to-DC converter. PWMs are disabled by writ-
ing zeros into the drive ratio fields in the PMPCON
Pump Control register.
NOTE:
To maximize power savings, the drive ratio
fields should be used to disable the PWMs,
instead of the FB pins. The clocks that
source the PWMs are disabled when the
drive ratio fields are zeroed.
3.19
IEEE 1149.1 compliant JTAG is provided with the
EP7212.
Table 24
shows what instructions are sup-
ported in the EP7212.
Boundary Scan
The INTEST function will not be supported for the
EP7212.
Additional user-defined instructions exist, but
these are not relevant to board-level testing. For
further information please refer to the
ARM DDI
0087E ARM720T
Data Sheet
.
As there are additional scan-chains within the
ARM720T processor, it is necessary to include a
scan-chain select function — shown as SCAN_N
in
Table 24
. To select a particular scan chain, this
function must be input to the TAP controller, fol-
lowed by the 4-bit scan chain identification code.
The identification code for the boundary scan chain
is 0011.
Note that it is only necessary to issue the SCAN_N
instruction if the device is already in the JTAG
mode. The boundary scan chain is selected as the
default on test-logic reset and any of the system re-
sets.
The contents of the device ID-register for the
EP7212 are shown in
Table 25
. This is equivalent
to 0x0F0F0F0F. Note this is the ID-code for the
ARM720T processor.
3.20
3.20.1
In-Circuit Emulation
Introduction
EmbeddedICE
is an extension to the architecture
of the ARM family of processors, and provides the
ability to debug cores that are deeply embedded
into systems. It consists of three parts:
1) A set of extensions to the ARM core
2) The EmbeddedICE macrocell, which provides
external access to the extensions
3) The EmbeddedICE interface, which provides
communication between the host computer and
the EmbeddedICE macrocell
The EmbeddedICE macrocell is programmed, in a
serial fashion, through the TAP controller on the
ARM via the JTAG interface. The EmbeddedICE
macrocell is by default disabled to minimize power
usage, and must be enabled at boot-up to support
this functionality.
Instruction
EXTEST
Code
0000
Description
Places the selected
scan chain in test
mode.
Connects the Scan
Path Register between
TDI and TDO
NOTE:
This instruc-
tion is included for
product testing only
and should never be
used.
Connects the ID regis-
ter between TDI and
TDO
Connects a 1-bit shift
register bit TDI and
TDO
SCAN_N
0010
SAMPLE / PRE-
LOAD
0011
IDCODE
1110
BYPASS
1111
Table 24. Instructions Supported in JTAG Mode
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP7212-CB-A 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
EP7212-CV-A 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:HIGH-PERFORMANCE, LOW-POWER SYSTEM-ON-CHIP WITH LCD CONTROLLER AND DIGITAL AUDIO INTERFACE(DAI)
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