參數(shù)資料
型號: EPC1064V
廠商: Electronic Theatre Controls, Inc.
英文描述: Configuration Devices for SRAM-Based LUT Devices
中文描述: 配置SRAM器件基于LUT的器件
文件頁數(shù): 23/28頁
文件大?。?/td> 380K
代理商: EPC1064V
Altera Corporation
23
Configuration Devices for ACEX, APEX, FLEX & Mercury Devices Data Sheet
Figure 9. EPC2 JTAG Waveforms
Table9
shows the timing parameters and values for configuration
devices.
Table 9. JTAG Timing Parameters & Values
Symbol
Parameter
Min
Max
Unit
t
JCP
t
JCH
t
JCL
t
JPSU
t
JPH
t
JPCO
t
JPZX
t
JPXZ
t
JSSU
t
JSH
t
JSCO
t
JSZX
t
JSXZ
TCK
clock period
100
ns
TCK
clock high time
50
ns
TCK
clock low time
50
ns
JTAG port setup time
20
ns
JTAG port hold time
45
ns
JTAG port clock to output
25
ns
JTAG port high impedance to valid output
25
ns
JTAG port valid output to high impedance
25
ns
Capture register setup time
20
ns
Capture register hold time
45
ns
Update register clock to output
25
ns
Update register high-impedance to valid output
25
ns
Update register valid output to high impedance
25
ns
TDO
TCK
t
JPZX
t
JPCO
t
JPH
t
JPXZ
t
JCP
t
JPSU
t
JCL
t
JCH
TDI
TMS
Signal
to Be
Captured
Signal
to Be
Driven
t
JSZX
t
JSSU
t
JSH
t
JSCO
t
JSXZ
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