參數(shù)資料
型號： EPC16QC100
廠商： Altera Corporation
英文描述： 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
中文描述： 2。增強(qiáng)型配置器件（EPC4，EPC8
文件頁數(shù)： 11/36頁
文件大?。?/td> 421K
代理商： EPC16QC100
Altera Corporation
August 2005
2–11
Configuration Handbook, Volume 2
Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
Figure 2–3. Concurrent Configuration of Multiple FPGAs in PS Mode (n = 8)
Notes to
Figure 2–3
:
(1)
Connect V
CC
to the same supply voltage as the configuration device.
(2)
The
nINIT_CONF
pin is available on enhanced configuration devices and has an internal pull-up resistor that is
always active. This means an external pull-up resistor is not required on the
nINIT_CONF
/
nCONFIG
line. The
nINIT_CONF
pin does not need to be connected if its functionality is not used. If
nINIT_CONF
is not used,
nCONFIG
must be pulled to V
CC
either directly or through a resistor.
(3)
The enhanced configuration devices’
OE
and
nCS
pins have internal programmable pull-up resistors. If internal
pull-up resistors are used, external pull-up resistors should not be used on these pins. The internal pull-up resistors
are used by default in the Quartus II software. To turn off the internal pull-up resistors, check the
Disable nCS and
OE pull-ups on configuration device
option when generating programming files.
(4)
For
PORSEL
,
PGM[]
, and
EXCLK
pin connections, refer to
Table 2–9
.
(5)
In the 100-pin PQFP package, you must externally connect the following pins:
C-A0
to
F-A0
,
C-A1
to
F-A1
,
C-A15
to
F-A15
,
C-A16
to
F-A16
, and
BYTE#
to V
CC
. Additionally, you must make the following pin connections in both
100-pin PQFP and 88-pin Ultra FineLine BGA packages:
C-RP#
to
F-RP#
,
C-WE#
to
F-WE#
,
TM1
to V
CC
,
TM0
to
GND, and
WP#
to V
CC
.
(6)
Connect the FPGA
MSEL[]
input pins to select the PS configuration mode. For details, refer to the appropriate
FPGA family chapter in the Configuration Handbook.
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
V
CC
GND
(3)
nCE
(3)
FPGA0
V
CC
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
nCE
DCLK
DATA0
nSTATUS
CONF_DONE
nCONFIG
GND
GND
FPGA1
FPGA7
Enhanced Configuration
Device
DCLK
DATA0
OE
nCS
nINIT_CONF
(2)
WE#C
RP#C
WE#F
RP#F
A[20..0]
RY/BY#
CE#
OE#
DQ[15..0]
DATA1
nCE
DATA 7
N.C.
N.C.
N.C.
N.C.
N.C.
(3)
(3)
EXCLK
PORSEL
PGM[2..0]
GND
TMO
WP#
BYTE#
(5)
TM1
V
CC
VCCW
C-A0
(5)
C-A1
(5)
C-A15
(5)
C-A16
(5)
A0-F
A1-F
A15-F
A16-F
MSEL
MSEL
MSEL
n
n
n
(6)
(6)
(6)
(1)
(1)
nCEO
N.C.
nCEO
N.C.
nCEO
N.C.
(1)
(4)
(4)
(4)
V
CC
(1)
相關(guān)PDF資料
PDF描述
EPC16QI100 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
EPC8xxx 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
EPC8QC100 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
EPC8QI100 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
EPC16xxx 435882001
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