參數(shù)資料
型號: EPC16QC100
廠商: Altera Corporation
英文描述: 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
中文描述: 2。增強型配置器件(EPC4,EPC8
文件頁數(shù): 26/36頁
文件大小: 421K
代理商: EPC16QC100
2–26
Configuration Handbook, Volume 2
Altera Corporation
August 2005
Programming & Configuration File Support
Alternatively, a power monitoring circuit or a power good signal can be
used to keep the FPGA’s
nCONFIG
pin asserted low until both supplies
have stabilized. This ensures the correct power up sequence for
successful configuration.
Programming &
Configuration
File Support
The Quartus II development software provides programming support for
the enhanced configuration device and automatically generates the POF
files for the EPC4, EPC8, and EPC16 devices. In a multi-device project, the
software can combine the SOF files for multiple Stratix series, Cyclone
series, APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX 10K FPGAs
into one programming file for the enhanced configuration device.
f
Refer to Using
Altera Enhanced Configuration Devices
, chapter 3 in volume
2 of the
Configuration
Handbook
or the
Software Settings
section in the
Configuration
Handbook
for details on generating programming files.
Enhanced configuration devices can be programmed in-system through
its industry-standard 4-pin JTAG interface. The ISP feature in the
enhanced configuration device provides ease in prototyping and
updating FPGA functionality.
After programming an enhanced configuration device in-system, FPGA
configuration can be initiated by including the enhanced configuration
device’s JTAG
INIT_CONF
instruction (
Table 2–10
).
The ISP circuitry in the enhanced configuration device is compliant with
the IEEE Std. 1532 specification. The IEEE Std. 1532 is a standard that
allows concurrent ISP between devices from multiple vendors.
Table 2–10. Enhanced Configuration Device JTAG Instructions (Part 1 of 2)
Note (1)
JTAG Instruction
OPCODE
Description
SAMPLE/PRELOAD 00 0101 0101 Allows a snapshot of the state of the enhanced configuration device pins
to be captured and examined during normal device operation and permits
an initial data pattern output at the device pins.
EXTEST
00 0000 0000 Allows the external circuitry and board-level interconnections to be tested
by forcing a test pattern at the output pins and capturing results at the
input pins.
BYPASS
11 1111 1111 Places the 1-bit bypass register between the
TDI
and the
TDO
pins, which
allow the BST data to pass synchronously through a selected device to
adjacent devices during normal device operation.
相關(guān)PDF資料
PDF描述
EPC16QI100 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
EPC8xxx 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
EPC8QC100 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
EPC8QI100 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
EPC16xxx 435882001
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