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參數(shù)資料
| 型號： | EPC8xxx |
| 廠商： | Altera Corporation |
| 英文描述： | 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet |
| 中文描述： | 2。增強型配置器件（EPC4，EPC8 |
| 文件頁數(shù)： | 15/36頁 |
| 文件大小： | 421K |
| 代理商： | EPC8XXX |
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Altera Corporation
August 2005
2–15
Configuration Handbook, Volume 2
Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet
Dynamic configuration or the page mode feature enables you to store a
minimum of two pages: a factory default or fail-safe configuration, and
an application configuration. The fail-safe configuration page could be
programmed during system production, while the application
configuration page could support remote or local updates. These remote
updates could add or enhance system features and performance.
However, with remote update capabilities comes the risk of possible
corruption of configuration data. In the event of such a corruption, the
system could automatically switch to the fail-safe configuration and
avoid system downtime.
The enhanced configuration device page mode feature works with the
Stratix Remote System Configuration feature, to enable intelligent remote
updates to your systems.
f
For more information on remotely updating Stratix FPGAs, refer to
Using Remote System Configuration with Stratix & Stratix GX Devices
in the
Stratix
Device
Handbook
.
The three
PGM[2..0]
input pins control which page is used for
configuration, and these pins are sampled at the start of each
configuration cycle when
OE
goes high. The page mode selection allows
you to dynamically reconfigure the functionality of your FPGA(s) by
switching the
PGM[2..0]
pins and asserting
nCONFIG
. Page 0 is defined
as the default page and the
PGM[2]
pin is the most significant bit (MSB).
1
The
PGM[2..0]
input pins must not be left floating on your
board, regardless of whether this feature is used or not. When
this feature is not used, connect the
PGM[2..0]
pins to GND to
select the default page 000.
The enhanced configuration device pages are dynamically sized regions
in memory. The start address and length of each page is programmed into
the option bit space of the flash memory during initial programming. All
subsequent configuration cycles will sample the
PGM[]
pins and use the
option bit information to jump to the start of the corresponding
configuration page. Each page must have configuration files for all
FPGAs in your system that are connected to that enhanced configuration
device.
For example, if your system requires three configuration pages and
includes two FPGAs, each page will store two SRAM Object Files (
.sof
)
for a total of six SOFs in the configuration device.
相關PDF資料 |
PDF描述 |
|---|---|
| EPC8QC100 | 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet |
| EPC8QI100 | 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet |
| EPC16xxx | 435882001 |
| EPC4QC100 | 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet |
| EPC4QI100 | 2. Enhanced Configuration Devices (EPC4, EPC8 & EPC16) Data Sheet |
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