參數資料
型號： EPF10K10
廠商： Altera Corporation
英文描述： EMBEDDED PROGRAMMABLE LOGIC FAMILY
中文描述： 嵌入式可編程邏輯系列
文件頁數： 47/120頁
文件大小： 1901K
代理商： EPF10K10
32
Altera Corporation
FLEX 10KE Embedded Programmable Logic Family Data Sheet
On all FLEX 10KE devices (except EPF10K50E and EPF10K200E), the
input path from the I/O pad to the FastTrack Interconnect has a
programmable delay element that can be used to guarantee a zero hold
time. EPF10K50S and EPF10K200S devices support this feature.
Depending on the placement of the IOE relative to what it is driving, the
designer may choose to turn on the programmable delay to ensure a zero
hold time or turn it off to minimize setup time. This feature is used to
reduce setup time for complex pin-to-register paths (e.g., PCI designs).
Each IOE selects the clock, clear, clock enable, and output enable controls
from a network of I/O control signals called the peripheral control bus.
The peripheral control bus uses high-speed drivers to minimize signal
skew across devices and provides up to 12 peripheral control signals that
can be allocated as follows:
s
Up to eight output enable signals
s
Up to six clock enable signals
s
Up to two clock signals
s
Up to two clear signals
If more than six clock enable or eight output enable signals are required,
each IOE on the device can be controlled by clock enable and output
enable signals driven by specific LEs. In addition to the two clock signals
available on the peripheral control bus, each IOE can use one of two
dedicated clock pins. Each peripheral control signal can be driven by any
of the dedicated input pins or the first LE of each LAB in a particular row.
In addition, a LE in a different row can drive a column interconnect, which
causes a row interconnect to drive the peripheral control signal. The chip-
wide reset signal resets all IOE registers, overriding any other control
signals.
When a dedicated clock pin drives IOE registers, it can be inverted for all
IOEs in the device. All IOEs must use the same sense of the clock. For
example, if any IOE uses the inverted clock, all IOEs must use the inverted
clock and no IOE can use the non-inverted clock. However, LEs can still
use the true or complement of the clock on a LAB-by-LAB basis.
The incoming signal may be inverted at the dedicated clock pin and will
drive all IOEs. For the true and complement of a clock to be used to drive
IOEs, drive it into both global clock pins. One global clock pin will supply
the true, and the other will supply the complement.
When the true and complement of a dedicated input drives IOE clocks,
two signals on the peripheral control bus are consumed, one for each
sense of the clock.
相關PDF資料
PDF描述
EPF10K100 EMBEDDED PROGRAMMABLE LOGIC FAMILY
EPF10K100A EMBEDDED PROGRAMMABLE LOGIC FAMILY
EPF10K20 EMBEDDED PROGRAMMABLE LOGIC FAMILY
EPF10K50 EMBEDDED PROGRAMMABLE LOGIC FAMILY
EP610I Classic EPLD Family
相關代理商/技術參數
參數描述
EPF10K100 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:EMBEDDED PROGRAMMABLE LOGIC FAMILY
EPF10K100A 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:1. Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet
EPF10K100ABC3561 制造商:ALTERA 功能描述:New
EPF10K100ABC356-1 功能描述:FPGA - 現場可編程門陣列 FPGA - Flex 10K 624 LABs 274 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
EPF10K100ABC356-1N 功能描述:FPGA - 現場可編程門陣列 FPGA - Flex 10K 624 LABs 274 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數量: 邏輯塊數量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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