參數(shù)資料
型號(hào): EPF10K130V
廠商: Altera Corporation
英文描述: EMBEDDED PROGRAMMABLE LOGIC FAMILY
中文描述: 嵌入式可編程邏輯系列
文件頁數(shù): 73/120頁
文件大?。?/td> 1901K
代理商: EPF10K130V
56
Altera Corporation
FLEX 10KE Embedded Programmable Logic Family Data Sheet
tCLR
LE register clear delay
tCH
Minimum clock high time from clock pin
tCL
Minimum clock low time from clock pin
Table 24. LE Timing Microparameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Condition
Table 25. IOE Timing Microparameters
Symbol
Parameter
Conditions
tIOD
IOE data delay
tIOC
IOE register control signal delay
tIOCO
IOE register clock-to-output delay
tIOCOMB
IOE combinatorial delay
tIOSU
IOE register setup time for data and enable signals before clock; IOE
register recovery time after asynchronous clear
tIOH
IOE register hold time for data and enable signals after clock
tIOCLR
IOE register clear time
tOD1
Output buffer and pad delay, slow slew rate = off, VCCIO = 3.3 V
C1 = 35 pF (2)
tOD2
Output buffer and pad delay, slow slew rate = off, VCCIO = 2.5 V
C1 = 35 pF (3)
tOD3
Output buffer and pad delay, slow slew rate = on
C1 = 35 pF (4)
tXZ
IOE output buffer disable delay
tZX1
IOE output buffer enable delay, slow slew rate = off, VCCIO = 2.5 V
C1 = 35 pF (2)
tZX2
IOE output buffer enable delay, slow slew rate = off, VCCIO = 3.5 V
C1 = 35 pF (3)
tZX3
IOE output buffer enable delay, slow slew rate = on
C1 = 35 pF (4)
tINREG
IOE input pad and buffer to IOE register delay
tIOFD
IOE register feedback delay
tINCOMB
IOE input pad and buffer to FastTrack Interconnect delay
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