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參數(shù)資料
| 型號： | EPF8282AV |
| 廠商： | Altera Corporation |
| 英文描述： | IRDA ENCODE/DECODE |
| 中文描述： | 系列可編程邏輯元件 |
| 文件頁數(shù)： | 24/61頁 |
| 文件大?。?/td> | 979K |
| 代理商： | EPF8282AV |
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24
Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
MultiVolt I/O Interface
The FLEX 8000 device architecture supports the MultiVolt I/O interface
feature, which allows EPF81500A, EPF81188A, EPF8820A, and EPF8636A
devices to interface with systems with differing supply voltages. These
devices in all packages—except for EPF8636A devices in 84-pin PLCC
packages—can be set for 3.3-V or 5.0-V I/O pin operation. These devices
have one set of V
CC
pins for internal operation and input buffers
(
VCCINT
), and another set for I/O output drivers (
VCCIO
).
The
VCCINT
pins must always be connected to a 5.0-V power supply. With
a 5.0-V V
CCINT
level, input voltages are at TTL levels and are therefore
compatible with 3.3-V and 5.0-V inputs.
The
VCCIO
pins can be connected to either a 3.3-V or 5.0-V power supply,
depending on the output requirements. When the
VCCIO
pins are
connected to a 5.0-V power supply, the output levels are compatible with
5.0-V systems. When the
VCCIO
pins are connected to a 3.3-V power
supply, the output high is at 3.3 V and is therefore compatible with 3.3-V
or 5.0-V systems. Devices operating with V
CCIO
levels lower than 4.75 V
incur a nominally greater timing delay of
t
OD2
instead of
t
OD1
. See
Table 7
on page 26
.
IEEE 1149.1
(JTAG)
Boundary-Scan
Support
The EPF8282A, EPF8282AV, EPF8636A, EPF8820A, and EPF81500A
devices provide JTAG BST circuitry. FLEX 8000 devices with JTAG
circuitry support the JTAG instructions shown in
Table 6
.
Figure 14
shows the timing requirements for the JTAG signals.
Table 6. EPF8282A, EPF8282AV, EPF8636A, EPF8820A & EPF81500A JTAG Instructions
JTAG Instruction
Description
SAMPLE/PRELOAD Allows a snapshot of the signals at the device pins to be captured and examined during
normal device operation, and permits an initial data pattern to be output at the device pins.
EXTEST
Allows the external circuitry and board-level interconnections to be tested by forcing a test
pattern at the output pins and capturing test results at the input pins.
BYPASS
Places the 1-bit bypass register between the
TDI
and
TDO
pins, which allows the BST
data to pass synchronously through the selected device to adjacent devices during
normal device operation.
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