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| 型號(hào)： | EPF8636A |
| 廠商： | Altera Corporation |
| 英文描述： | PROGRAMMABLE LOGIC DEVICES FAMILY |
| 中文描述： | 系列可編程邏輯元件 |
| 文件頁數(shù)： | 16/61頁 |
| 文件大?。?/td> | 979K |
| 代理商： | EPF8636A |
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16
Altera Corporation
FLEX 8000 Programmable Logic Device Family Data Sheet
FastTrack Interconnect
In the FLEX 8000 architecture, connections between LEs and device I/O
pins are provided by the FastTrack Interconnect, a series of continuous
horizontal (row) and vertical (column) routing channels that traverse the
entire FLEX 8000 device. This device-wide routing structure provides
predictable performance even in complex designs. In contrast, the
segmented routing structure in FPGAs requires switch matrices to
connect a variable number of routing paths, which increases the delays
between logic resources and reduces performance.
The LABs within FLEX 8000 devices are arranged into a matrix of
columns and rows. Each row of LABs has a dedicated row interconnect
that routes signals both into and out of the LABs in the row. The row
interconnect can then drive I/O pins or feed other LABs in the device.
Figure 8
shows how an LE drives the row and column interconnect.
Figure 8. FLEX 8000 LAB Connections to Row & Column Interconnect
LE1
LE2
Row Channels
Note (1)
16 Column
Channels
Each LE drives up to
two column channels.
to Local
Feedback
to Local
Feedback
Each LE drives one
row channel.
Note:
(1)
See
Table 4
for the number of row channels.
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