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參數(shù)資料
| 型號： | EPF8820A |
| 廠商： | Altera Corporation |
| 英文描述： | LED, BLUE 6 MCD 20 MA |
| 中文描述： | 系列可編程邏輯元件 |
| 文件頁數(shù)： | 21/61頁 |
| 文件大?。?/td> | 979K |
| 代理商： | EPF8820A |
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Altera Corporation
21
FLEX 8000 Programmable Logic Device Family Data Sheet
Figure 12. FLEX 8000 Column-to-IOE Connections
In addition to general-purpose I/O pins, FLEX 8000 devices have four
dedicated input pins. These dedicated inputs provide low-skew, device-
wide signal distribution, and are typically used for global clock, clear, and
preset control signals. The signals from the dedicated inputs are available
as control signals for all LABs and I/O elements in the device. The
dedicated inputs can also be used as general-purpose data inputs because
they can feed the local interconnect of each LAB in the device.
Signals enter the FLEX 8000 device either from the I/O pins that provide
general-purpose input capability or from the four dedicated inputs. The
IOEs are located at the ends of the row and column interconnect channels.
I/O pins can be used as input, output, or bidirectional pins. Each I/O pin
has a register that can be used either as an input register for external data
that requires fast setup times, or as an output register for data that
requires fast clock-to-output performance. The MAX+PLUS II Compiler
uses the programmable inversion option to automatically invert signals
from the row and column interconnect when appropriate.
The clock, clear, and output enable controls for the IOEs are provided by
a network of I/O control signals. These signals can be supplied by either
the dedicated input pins or by internal logic. The IOE control-signal paths
are designed to minimize the skew across the device. All control-signal
sources are buffered onto high-speed drivers that drive the signals around
the periphery of the device. This “peripheral bus” can be configured to
provide up to four output enable signals (10 in EPF81500A devices), and
up to two clock or clear signals.
Figure 13
shows how two output enable
signals are shared with one clock and one clear signal.
IOE
IOE
8
8
16
Column Interconnect
Each IOE is
driven by an
8-to-1
multiplexer.
Each IOE can drive
up to two column
signals.
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| EPF8820ABC225-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EPF8820ABC225-4 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Flex 8000 84 LABs 152 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EPF8820ABI225-3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EPF8820AGI192-3 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| EPF8820AQC144-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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