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參數資料
| 型號： | EPM7096 |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Logic Device Family |
| 中文描述： | 可編程邏輯器件系列 |
| 文件頁數： | 40/62頁 |
| 文件大小： | 1173K |
| 代理商： | EPM7096 |
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40
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
These values are specified under the recommended operating conditions shown in
Table 11
. See
Figure 13
for more
information on switching waveforms.
(2)
This minimum pulse width for preset and clear applies for both global clear and array controls. The
t
parameter
must be added to this minimum width if the clear or reset signal incorporates the
t
LAD
parameter into the signal
path.
(3)
This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
parameter applies for both global and array clocking.
(4)
These parameters are measured with a 16-bit loadable, enabled, up/ down counter programmed into each LAB.
(5)
The
f
values represent the highest frequency for pipelined data.
(6)
Operating conditions: V
= 3.3 V
±
10
%
for commercial and industrial use.
(7)
For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices,
these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these
devices, add an additional 0.1 ns to the PIA timing value.
(8)
The
t
parameter must be added to the
t
LAD
, t
LAC
, t
IC
, t
EN
,
t
SEXP
,
t
ACL
, and
t
CPPW
parameters for macrocells
running in the low-power mode.
t
H
t
FSU
Register hold time
1.7
2.0
2.0
3.0
ns
Register setup time of fast
input
1.9
1.8
3.0
3.0
ns
t
FH
Register hold time of fast
input
0.6
0.7
0.5
0.5
ns
t
RD
t
COMB
t
IC
t
EN
t
GLOB
t
PRE
t
CLR
t
PIA
t
LPA
Register delay
1.2
1.6
1.0
2.0
ns
Combinatorial delay
0.9
1.0
1.0
2.0
ns
Array clock delay
2.7
3.3
3.0
5.0
ns
Register enable time
2.6
3.2
3.0
5.0
ns
Global control delay
1.6
1.9
1.0
1.0
ns
Register preset time
2.0
2.4
2.0
3.0
ns
Register clear time
2.0
2.4
2.0
3.0
ns
PIA delay
(7)
1.1
1.3
1.0
1.0
ns
Low-power adder
(8)
12.0
11.0
10.0
11.0
ns
Table 27. EPM7064S Internal Timing Parameters (Part 2 of 2)
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-5
-6
-7
-10
Min
Max
Min
Max
Min
Max
Min
Max
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相關代理商/技術參數 |
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|---|---|
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| EPM7096JC84 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP Complex PLD |
| EPM7096JC84-2 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UV-Erasable/OTP Complex PLD |
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