參數(shù)資料
型號(hào): EPM7256B
廠商: Altera Corporation
英文描述: Programmable Logic Device Family(MAX7000B可編程邏輯系列器件)
中文描述: 可編程邏輯器件系列(MAX7000B可編程邏輯系列器件)
文件頁(yè)數(shù): 22/125頁(yè)
文件大?。?/td> 1053K
代理商: EPM7256B
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)當(dāng)前第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)
22
Altera Corporation
MAX 7000B Programmable Logic Device Family Data Sheet
Preliminary Information
Programmable Pull-Up Resistor
Each MAX 7000B device I/ O pin provides an optional programmable
pull-up resistor during user mode. When this feature is enabled for an I/ O
pin, the pull-up resistor (typically 50 k
) weakly holds the output to
V
CCIO
level.
Bus Hold
Each MAX 7000B device I/ O pin provides an optional bus-hold feature.
When this feature is enabled for an I/ O pin, the bus-hold circuitry weakly
holds the signal at its last driven state. By holding the last driven state of
the pin until the next input signals is present, the bus-hold feature can
eliminate the need to add external pull-up or pull-down resistors to hold
a signal level when the bus is tri-stated. The bus-hold circuitry also pulls
undriven pins away from the input threshold voltage where noise can
cause unintended high-frequency switching. This feature can be selected
individually for each I/ O pin. The bus-hold output will drive no higher
than V
CCIO
to prevent overdriving signals.
The bus-hold circuitry weakly pulls the signal level to the last driven state
through a resistor with a nominal resistance (RBH) of approximately
8.5 k
.
Table 10
gives specific sustaining current that will be driven
through this resistor and overdrive current that will identify the next
driven input level. This information is provided for each VCCIO voltage
level.
The bus-hold circuitry is active only during user operation. At power-up,
the bus-hold circuit initializes its initial hold value as V
CC
approaches the
recommended operation conditions. When transitioning from ISP to User
Mode with bus hold enabled, the bus-hold circuit captures the value
present on the pin at the end of programming.
Table 10. Bus Hold Parameters
Parameter
Conditions
VCCIO Level
Units
1.8 V
2.5 V
3.3 V
Min
Max
Min
Max
Min
Max
Low sustaining current
High sustaining current
Low overdrive current
High overdrive current
V
IN
> V
IL
(max)
V
IN
< V
IH
(min)
0 V < V
IN
< V
CCIO
0 V < V
IN
< V
CCIO
30
–30
50
–50
70
–70
μ
A
μ
A
μ
A
μ
A
200
–295
300
–435
500
–680
相關(guān)PDF資料
PDF描述
EPM7032LC44-15 Programmable Logic Device Family
EPM7064B Programmable Logic Device
EPM7128A Programmable Logic Device
EPM7256A Programmable Logic Device
EPM7032AE Programmable Logic Device
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EPM7256BBC169-10 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EPM7256BBC169-5 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EPM7256BBC169-7 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EPM7256BBI169-10 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
EPM7256BBI169-5 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC