參數(shù)資料
型號(hào): EPM7256B
廠商: Altera Corporation
英文描述: Programmable Logic Device Family(MAX7000B可編程邏輯系列器件)
中文描述: 可編程邏輯器件系列(MAX7000B可編程邏輯系列器件)
文件頁數(shù): 85/125頁
文件大?。?/td> 1053K
代理商: EPM7256B
84
Altera Corporation
MAX 7000B Programmable Logic Device Family Data Sheet
Preliminary Information
Notes to tables:
(1)
This pin can function as either a JTAG port or a user I/O pin. If the device is configured to use the JTAG ports for
in-system programming, this pin is not available as a user I/O pin.
(2)
This pin may function as either a
VREF
pin or a user I/O pin. If this pin is programmed to be a
VREF
pin for using
the advanced I/O standards, this pin is not available as a user I/O pin.
(3)
The user I/O pin count includes dedicated input pins and all I/O pins.
(4)
EPM7512B devices in the 208-pin PQFP package support vertical migration from EPM7256E, EPM7256S, and
EPM7256B devices. EPM7512B devices contain additional I/O pins which are no connects on the EPM7256E,
EPM7256S, and EPM7256B devices. To support these additional I/O pins, EPM7512B devices have two additional
VCCIO1
(pin 105),
VCCIO2
(pin 207) and
GNDIO
(pins 51 and 158) pins that are no-connect pins on the EPM7256E,
EPM7256S, and EPM7256B devices. To achieve vertical migration between the EPM7256B and EPM7512B devices,
the no-connect pin 105 may be tied to
VCCIO1
, pin 207 may be tied to
VCCIO2
, and pins 51 and 158 may be tied to
GNDIO
on EPM7256B devices.
P
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
65
64
62
61
60
59
58
57
56
55
G
G
G
G
G
G
G
G
G
G
R11
P11
N11
M11
T12
R12
M12
P12
N12
T13
G
G
G
G
G
G
G
G
G
G
G (100 mA) 2
G (100 mA) 2
H (200 mA)
H (200 mA)
H (200 mA)
H (200 mA)
H (200 mA)
H (200 mA)
H (200 mA)
H (200 mA)
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Table 50. EPM7256B I/O Pin-Outs & I/O Standards (Part 9 of 9)
LAB
MC
208-Pin
PQFP
(4)
IOGND
group for
208-Pin PQFP
(200 mA)
256-Pin
FineLine
BGA
IOGND
group for
256-Pin
FineLine BGA
(200 mA)
IOVCC
group for
208 &
256-Pin
Packages
I/O
Bank
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