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參數(shù)資料
| 型號： | EPM9480 |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Logic Device Family(MAX9000可編程邏輯系列器件) |
| 中文描述： | 可編程邏輯器件系列（MAX9000可編程邏輯系列器件） |
| 文件頁數(shù)： | 32/41頁 |
| 文件大?。?/td> | 604K |
| 代理商： | EPM9480 |
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32
Altera Corporation
MAX 9000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
These values are specified under the MAX 9000 device recommended operating conditions, shown in
Table 12 on
page 24
.
(2)
See
Application Note 77 (Understanding MAX 9000 Timing)
in this data book for more information on test conditions
for
t
PD1
and
t
PD2
delays.
(3)
This parameter is a guideline that is sample-tested only. It is based on extensive device characterization. This
parameter applies for both global and array clocking as well as both macrocell and I/O cell registers.
(4)
Measured with a 16-bit loadable, enabled, up/down counter programmed in each LAB.
(5)
The
t
LPA
parameter must be added to the
t
LOCAL
parameter for macrocells running in low-power mode
.
(6)
The
t
ROW
,
t
COL,
and
t
IOC
delays are worst-case values for typical applications. Post-compilation timing simulation
or timing analysis is required to determine actual worst-case performance.
Power
Consumption
The supply power (P) versus frequency (
f
MAX
) for MAX 9000 devices can
be calculated with the following equation:
P = P
INT
+ P
IO
= I
CCINT
×
V
CC
+ P
IO
The P
IO
value, which depends on the device output load characteristics
and switching frequency, can be calculated using the guidelines given in
Application Note 74 (Evaluating Power for Altera Devices)
in this data book.
The I
CCINT
value depends on the switching frequency and the application
logic.
The I
CCINT
value is calculated with the following equation:
I
CCINT
= (A
×
MC
TON
) + [B
×
(MC
DEV
–
MC
TON
)] + (C
×
MC
USED
×
f
MAX
×
tog
LC
)
Table 21. Interconnect Delays
Symbol
Parameter
Conditions
Speed Grade
Unit
-10
-15
-20
Min
Max
Min
Max
Min
Max
t
LOCAL
t
ROW
t
COL
t
DIN_D
t
DIN_CLK
t
DIN_CLR
t
DIN_IOC
LAB local array delay
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
FastTrack row delay
(6)
0.9
1.4
2.0
FastTrack column delay
(6)
0.9
1.7
3.0
Dedicated input data delay
4.0
4.5
5.0
Dedicated input clock delay
2.7
3.5
4.0
Dedicated input clear delay
4.5
5.0
5.5
Dedicated input I/O register
clock delay
2.5
3.5
4.5
t
DIN_IO
Dedicated input I/O register
control delay
5.5
6.0
6.5
ns
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