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參數(shù)資料
| 型號： | EPM9560A |
| 廠商： | Altera Corporation |
| 英文描述： | Programmable Logic Device Family(MAX9000可編程邏輯系列器件) |
| 中文描述： | 可編程邏輯器件系列（MAX9000可編程邏輯系列器件） |
| 文件頁數(shù)： | 19/41頁 |
| 文件大?。?/td> | 604K |
| 代理商： | EPM9560A |
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Altera Corporation
19
MAX 9000 Programmable Logic Device Family Data Sheet
The
VCCIO
pins can be connected to either a 3.3-V or 5.0-V power supply,
depending on the output requirements. When the
VCCIO
pins are
connected to a 5.0-V power supply, the output levels are compatible with
5.0-V systems. When the
VCCIO
pins are connected to a 3.3-V power
supply, the output high is at 3.3 V and is therefore compatible with 3.3-V
or 5.0-V systems. Devices operating with V
CCIO
levels lower than 4.75 V
incur a nominally greater timing delay of
t
OD2
instead of
t
OD1
.
In-System
Programma-
bility (ISP)
MAX 9000 devices can be programmed in-system through a 4-pin JTAG
interface. ISP offers quick and efficient iterations during design
development and debug cycles. The MAX 9000 architecture internally
generates the 12.0-V programming voltage required to program EEPROM
cells, eliminating the need for an external 12.0-V power supply to
program the devices on the board. During ISP, the I/O pins are tri-stated
to eliminate board conflicts.
ISP simplifies the manufacturing flow by allowing the devices to be
mounted on a printed circuit board with standard pick-and-place
equipment before they are programmed. MAX 9000 devices can be
programmed by downloading the information via in-circuit testers,
embedded processors, or the Altera BitBlaster, ByteBlaster, or
ByteBlasterMV download cable. (The ByteBlaster cable is obsolete and has
been replaced by the ByteBlasterMV cable, which can interface with 2.5-V,
3.3-V, and 5.0-V devices.) Programming the devices after they are placed
on the board eliminates lead damage on high pin-count packages (e.g.,
QFP packages) due to device handling. MAX 9000 devices can also be
reprogrammed in the field (i.e., product upgrades can be performed in the
field via software or modem).
In-system programming can be accomplished with either an adaptive or
constant algorithm. An adaptive algorithm reads information from the
unit and adapts subsequent programming steps to achieve the fastest
possible programming time for that unit. Because some in-circuit testers
platforms have difficulties supporting an adaptive algorithm, Altera
offers devices tested with a constant algorithm. Devices tested to the
constant algorithm are marked with an “F” suffix in the ordering code.
Programming
with External
Hardware
MAX 9000 devices can be programmed on Windows-based PCs with an
Altera Logic Programmer card, the Master Programming Unit (MPU),
and the appropriate device adapter. The MPU performs continuity
checking to ensure adequate electrical contact between the adapter and
the device.
f
For more information, see the
Altera Programming Hardware
Data Sheet
.
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| EPM9560ABI356-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| EPM9560ARC208-10 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 9000 560 Macro 153 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| EPM9560ARC208-10N | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 9000 560 Macro 153 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
| EPM9560ARC240-10 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 9000 560 Macro 191 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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