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參數(shù)資料
| 型號： | EV0060 |
| 廠商： | Monolithic Power Systems, Inc. |
| 英文描述： | 1.2A Synchronous Rectified Step-Down Converter |
| 中文描述： | 1.2A的同步整流降壓轉(zhuǎn)換器 |
| 文件頁數(shù)： | 7/11頁 |
| 文件大?。?/td> | 309K |
| 代理商： | EV0060 |
MP1567 – 1.2A SYNCHRONOUS RECTIFIED STEP-DOWN CONVERTER
MP1567 Rev. 2.3
1/3/2006
www.MonolithicPower.com
7
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
2006 MPS. All Rights Reserved.
TM
output voltage ripple is mostly independent of
the ESR. The output voltage ripple is estimated
to be:
2
SW
LC
IN
RIPPLE
V
f
f
V
4
×
×
=
Where V
RIPPLE
is the output ripple voltage, V
IN
is
the input voltage, f
LC
is the resonant frequency
of the LC filter and f
SW
is the switching
frequency. In the case of tantalum or low-ESR
electrolytic capacitors, the ESR dominates the
impedance at the switching frequency, and so
the output ripple is calculated as:
ESR
RIPPLE
V
R
I
×
=
Where
I is the inductor ripple current, and
R
ESR
is the equivalent series resistance of the
output capacitors.
Choose an output capacitor to satisfy the output
ripple requirements of the design. A 10
μ
F
ceramic
capacitor
is
applications.
suitable
for
most
Selecting the Inductor
The inductor is required to supply constant
current to the output load while being driven by
the switched input voltage. A larger value
inductor results in less ripple current that will
results in lower output ripple voltage. However,
the larger value inductor has a larger physical
size, higher series resistance and/or lower
saturation current. Choose an inductor that
does not saturate under the worst-case load
conditions. A good rule for determining the
inductance is to allow the peak-to-peak ripple
current to be approximately 30% of the
maximum load current. Make sure that the peak
inductor current (the load current plus half the
peak-to-peak inductor ripple current) is below
2A to prevent loss of regulation due to the
current limit.
Calculate the required inductance value by the
equation:
I
f
V
)
V
V
(
×
V
L
SW
IN
OUT
IN
OUT
×
×
=
Compensation
The system stability is controlled through the
COMP pin. COMP is the output of the internal
transconductance error amplifier. A series
capacitor-resistor combination sets a pole-zero
combination to control the characteristics of the
control system.
The DC loop gain is:
×
×
×
=
OUT
V
FB
LOAD
CS
VEA
VDC
V
R
G
A
A
Where A
VEA
is the transconductance error
amplifier voltage gain, G
CS
is the current sense
gain (roughly the output current divided by the
voltage at COMP) and R
LOAD
is the load
resistance (V
OUT
/I
OUT
where I
OUT
is the output
load current)
The system has 2 poles of importance, one is
due to the compensation capacitor (C3), and
the other is due to the load resistance and the
output capacitor (C2). The first is:
3
C
A
2
G
f
VEA
EA
1
P
×
×
π
=
Where P1 is the first pole and G
EA
is the error
amplifier transconductance (300
μ
A/V). The
second is:
2
C
R
2
1
f
LOAD
2
P
×
×
π
=
The system has one zero of importance, due to
the compensation capacitor (C3) and the
compensation resistor (R3). The zero is:
3
C
3
R
2
1
f
1
Z
×
×
π
=
If large value capacitors with relatively high
equivalent-series-resistance (ESR) are used,
the zero due to the capacitance and ESR of the
output capacitor can be compensated by a third
pole set by R3 and C4. This pole is:
4
C
3
R
2
1
f
3
P
×
×
π
=
The system crossover frequency (the frequency
where the loop gain drops to 1, or 0dB) is
important. Set the crossover frequency to
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