參數(shù)資料
型號(hào)： EV4101
廠商： LSI Corporation
英文描述： 32-bit Microprocessor that Executes MIPS I,a Subset of MIPS II,and a Subset of the MIPS16 Instructions.(32位微處理器（執(zhí)行MIPS I,MIPS II的子集,MIPS16的子集指令）)
中文描述： 32位微處理器中執(zhí)行MIPS的我，一個(gè)子集的MIPS的第二，以及對(duì)MIPS16指令集。（32位微處理器（執(zhí)行MIPS的我，MIPS的二的子集，MIPS16的子集指令））
文件頁數(shù)： 10/68頁
文件大?。?/td> 545K
代理商： EV4101
10
TinyRISC
EV4101 Microprocessor Reference Device Technical Summary
UD
User Mode Debug Event Detection Enable
Setting UD enables debug breaks in User Mode. UD and
KD always contain the same value. Setting either bit sets
both bits.
30
KD
Kernel Mode Debug Event Detection Enable
Setting KD enables debug breaks in Kernel Mode. UD
and KD always contain the same value. Setting either bit
sets both bits.
29
Res
Reserved Bits
These bits are hard wired to zero. Software should
always write zeros to these bits.
28, [21:5]
DW
Data Write Enable
If DAE is enabled, setting DW enables data write event
detection.
27
DR
Data Read Enable
If DAE is enabled, setting DR enables data read event
detection.
26
DAE
Data Access Breakpoint Enable
Setting DAE enables data address breakpoint debug
events.
25
PCE
Program Counter Breakpoint Enable
Setting PCE enables program counter breakpoint debug
events.
24
DE
Debug Enable
Setting DE enables the debugger. Clearing DE disables
the debugger.
23
IBD
Internal Break Disable
Setting IBD disables internal breaks. Clearing IBD
enables internal breaks. When IBD is set, the DBX does
not assert the DBREAK_BBEP signal on a debug event.
22
W
Write Reference Status
The DBX sets this bit when it has detected a data write
debug condition. This bit can only be cleared by software.
4
R
Read Reference Status
The DBX sets this bit when it has detected a data read-
debug condition. This bit can only be cleared by software.
3
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