參數(shù)資料
型號: EV4101
廠商: LSI Corporation
英文描述: 32-bit Microprocessor that Executes MIPS I,a Subset of MIPS II,and a Subset of the MIPS16 Instructions.(32位微處理器(執(zhí)行MIPS I,MIPS II的子集,MIPS16的子集指令))
中文描述: 32位微處理器中執(zhí)行MIPS的我,一個子集的MIPS的第二,以及對MIPS16指令集。(32位微處理器(執(zhí)行MIPS的我,MIPS的二的子集,MIPS16的子集指令))
文件頁數(shù): 14/68頁
文件大?。?/td> 545K
代理商: EV4101
14
TinyRISC
EV4101 Microprocessor Reference Device Technical Summary
Table 7 shows the format of the MFD Instruction. The MFD Instruction is
not available from MIPS16 code.
MTD Instruction –
The Move To Debug (MTD) Instruction loads the
contents of General Register
rs
into a DBX Register
dr
. This instruction
is only valid if
dr
= 7, 18, 19, 20, or 21. All other
dr
values are undefined.
Operation: T: DEBUG[dr] <- GPR[rs]
Exceptions None
Table 8 shows the format of the MTD Instruction. The MTD Instruction is
not available from MIPS16 code.
4.1.3 Breakpoints
This section describes the operation of the DBX Building Block in more
detail.
When a breakpoint occurs, the DBX sets the proper status bit. All status
bits are sticky—they are not cleared by hardware, and can only be
cleared by software.
Breakpoints are only detected if the TR4101 actually executes the
breaking instruction, thus breakpoints can be placed freely in the code.
For example, a breakpoint placed at an instruction following any MIPS16
branch will only be detected if the branch is not taken, as one would
expect, from a programmer’s point of view. The general rule is that
breakpoints are only reported for instructions that complete their execute
stage, or for instructions that would have completed the stage were it not
for the Bus Error caused by the DBX.
In addition, breakpoints are reported in the order they occur in the code.
A data breakpoint followed by an instruction breakpoint results in the
Table 7
MFD Instruction (MIPS II format)
31
26 25
21 20
16 15
11 10
0
MFD = 011111
2
rs = 00000
2
rt
dr
0
Table 8
MTD Instruction (MIPS II format)
31
26 25
21 20
16 15
11 10
0
MTD = 011110
2
rs
rt = 00000
2
dr
0
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