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參數(shù)資料
| 型號： | EV4101 |
| 廠商： | LSI Corporation |
| 英文描述： | 32-bit Microprocessor that Executes MIPS I,a Subset of MIPS II,and a Subset of the MIPS16 Instructions.(32位微處理器（執(zhí)行MIPS I,MIPS II的子集,MIPS16的子集指令）) |
| 中文描述： | 32位微處理器中執(zhí)行MIPS的我，一個子集的MIPS的第二，以及對MIPS16指令集。（32位微處理器（執(zhí)行MIPS的我，MIPS的二的子集，MIPS16的子集指令）） |
| 文件頁數(shù)： | 15/68頁 |
| 文件大?。?/td> | 545K |
| 代理商： | EV4101 |
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TinyRISC
EV4101 Microprocessor Reference Device Technical Summary
15
data breakpoint being reported first, even though the instruction fetch
address following the data load/store transaction actually appears on the
CBus first.
Data Write Breakpoint –
A data write breakpoint occurs when the
TR4101 writes data to an address that matches all the bits of the BDA
Register not masked by the BDAM Register.
The DE, DW, and DAE bits of the DCS Register enable data write
breakpoints. The BDA and BDAM registers must be properly loaded
before the breakpoint is enabled. When the data write breakpoint occurs
and the IBD and TR bits of the DCS Register are enabled, the TR4101
signals a DBus Error. The EPC Register then points to the offending
write instruction unless the write instruction was executed in a delay slot.
In this case, EPC points to the jump or branch instruction instead. The
data write instruction and all previous instructions complete execution.
Data Read Breakpoint –
A data read breakpoint occurs when the
TR4101 reads data (not an instruction fetch) from an address that
matches all of the bits of the BDA Register not masked by the BDAM
Register.
The DE, DR, and DAE bits of the DCS Register enable data read
breakpoints. The BDA and BDAM registers must be properly loaded
before the breakpoint is enabled. When the data read breakpoint occurs
and the IBD and TR bits of the DCS Register are enabled, the TR4101
signals a DBus Error. The EPC Register then points to the offending read
instruction unless the read instruction was executed in a delay slot. In
this case, EPC points to the jump or branch instruction instead. All
previous instructions complete execution. The data read instruction is
completed if the data is not contained in cache, and is not completed if
the data is contained in cache.
Program Counter Breakpoint –
A program counter breakpoint occurs
when the TR4101 is about to execute an instruction whose address and
mode matches all the bits of the BPC Register not masked by the BPCM
Register.
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