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參數(shù)資料
| 型號(hào)： | EV4101 |
| 廠商： | LSI Corporation |
| 英文描述： | 32-bit Microprocessor that Executes MIPS I,a Subset of MIPS II,and a Subset of the MIPS16 Instructions.(32位微處理器（執(zhí)行MIPS I,MIPS II的子集,MIPS16的子集指令）) |
| 中文描述： | 32位微處理器中執(zhí)行MIPS的我，一個(gè)子集的MIPS的第二，以及對(duì)MIPS16指令集。（32位微處理器（執(zhí)行MIPS的我，MIPS的二的子集，MIPS16的子集指令）） |
| 文件頁(yè)數(shù)： | 18/68頁(yè) |
| 文件大?。?/td> | 545K |
| 代理商： | EV4101 |
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18
TinyRISC
EV4101 Microprocessor Reference Device Technical Summary
Full-duplex operation, fixed for 8 data bits, 1 stop bit, and no parity
bit.
Clock at 16 times the bit rate to define the receiving (Rx) and
transmitting (Tx) rates. The clock is common for Rx and Tx, and may
either be an external clock or be generated internally from the
system clock.
An Rx ready signal to indicate that one byte of data has been
received and is in the one-byte input buffer.
Separate status and data registers for Rx and Tx. The Rx Status
Register contains one bit that indicates the received data is in the
SerialICE port, and one bit that indicates an overrun in the Rx input
buffer. The Tx Status Register contains one bit that indicates the
SerialICE port is ready to transmit data.
Interrupt possible when new data is received.
Serial-receive and clock-input lines that require no active signal when
the SerialICE port is unused.
4.2.1 Registers
All SerialICE port registers are memory mapped, as shown in Table 9.
The base address for the SerialICE port register block is in the uncached
kseg1 and is set to 0xBFFF0200.
All register transactions are read transactions with 0 in bits [31:8], and
data in bits [7:0]. The register bits are mapped with bit 31 to BDATAP[31],
bit 30 to BDATAP[30], and so forth. Write transactions to read-only
registers are ignored, and read transactions from write-only registers
return undefined data.
Table 9
SerialICE Port Register Addresses
Address
Access
Register
0xBFFF0200
Read
Receive (Rx) Status Register
0xBFFF0200
Write
Receive (Rx) Setup Register
0xBFFF0204
Read
Receive (Rx) Data Register
0xBFFF0208
Read
Transmit (Tx) Status Register
0xBFFF020C
Write
Transmit (Tx) Data Register
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