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參數(shù)資料
| 型號： | EV4101 |
| 廠商： | LSI Corporation |
| 英文描述： | 32-bit Microprocessor that Executes MIPS I,a Subset of MIPS II,and a Subset of the MIPS16 Instructions.(32位微處理器（執(zhí)行MIPS I,MIPS II的子集,MIPS16的子集指令）) |
| 中文描述： | 32位微處理器中執(zhí)行MIPS的我，一個(gè)子集的MIPS的第二，以及對MIPS16指令集。（32位微處理器（執(zhí)行MIPS的我，MIPS的二的子集，MIPS16的子集指令）） |
| 文件頁數(shù)： | 21/68頁 |
| 文件大?。?/td> | 545K |
| 代理商： | EV4101 |
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TinyRISC
EV4101 Microprocessor Reference Device Technical Summary
21
Reserved
Reserved Bits
These bits are reserved. They are read as zeros.
[31:1]
TxRDY
Tx Ready
This bit is set to 1 when the byte in the Tx Data Register
has been transmitted and the Tx Data Register is ready
for the next byte. The bit is cleared to 0 by a write to the
Tx Data Register. The bit is set to 1 at reset.
0
Transmit (Tx) Data Register –
The Tx Data Register, shown in
Table 14, holds transmission data. The register is a write-only register.
Reserved
Reserved Bits
These bits are reserved. Write transactions to these bits
are ignored.
[31:8]
TxData
Transmitted Bit Stream
The Tx Data Register may be written with data to be
transmitted on ICETXP, provided that the TxRDY bit in the
Tx Status Register is set. A write to the register is ignored
when the TxRDY bit is cleared.
[7:0]
4.3 BBCC Overview
The EV4101 has a 16 Kbyte two-way set associative I-cache. Each
I-cache set (8 Kbyte each) contains 512 four-word lines. The EV4101
also has a 8 Kbyte D-cache, which also consists of 512 four-word lines.
Each line in the cache has a 19-bit tag and four valid bits. The D-cache
is write-through. Each cache set can be individually enabled or disabled
by setting the ICEN, IS1EN, and DCEN control bits of the System
Configuration Register (SCR).
Table 14
Tx Data Register
31
8
7
0
Reserved
TxData
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