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參數(shù)資料
| 型號(hào)： | EV4101 |
| 廠商： | LSI Corporation |
| 英文描述： | 32-bit Microprocessor that Executes MIPS I,a Subset of MIPS II,and a Subset of the MIPS16 Instructions.(32位微處理器（執(zhí)行MIPS I,MIPS II的子集,MIPS16的子集指令）) |
| 中文描述： | 32位微處理器中執(zhí)行MIPS的我，一個(gè)子集的MIPS的第二，以及對(duì)MIPS16指令集。（32位微處理器（執(zhí)行MIPS的我，MIPS的二的子集，MIPS16的子集指令）） |
| 文件頁數(shù)： | 28/68頁 |
| 文件大?。?/td> | 545K |
| 代理商： | EV4101 |
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TinyRISC
EV4101 Microprocessor Reference Device Technical Summary
4.4.4 Inpage Writes
The BBCC requests back-to-back write transactions if possible. The
PGSZ field of the SCR determines the page size that is used in
determining whether to prioritize the next write transaction. The EV4101
asserts a Write Burst Request if a pending write is in the same page. If
the Write Burst Acknowledge is received by the EV4101, the next
transaction will be the inpage write. The write transaction still appears as
two separate transactions (as opposed to a burst write).
4.4.5 Write Buffer
The EV4101 has a configurable depth write buffer. The WRBUF bit in the
SCR configures the write buffer depth as one or four deep. If the Write
Buffer depth is four, the TR4101 can execute up to four Store Word (SW)
instructions and not be stalled. The SWs are held in the write buffer until
the BBCC can service them.
4.4.6 Read Priority
The BBCC can be configured to prioritize Load Word (LW) instructions
over a SW that is already in the write buffer. If the RDPRI bit in the SCR
is one, the BBCC services a LW before a SW, even if the microprocessor
requested the SW earlier.
4.4.7 Snooping
The BBCC can be configured to snoop when the EV4101 is not the
master. Two control bits ISNPEN and DSNPEN control whether snooping
is done by the BBCC. If ISNPEN is set, then the I-caches are snooped
whenever the external master does a write transaction. Similarly, the
SDNPEN controls data cache snooping. If the address of the write
transaction matches the cache line, then the entire cache line is
invalidated. The I-cache or D-cache snoop takes two cycles. Snooping
both caches takes four cycles. The EV4101 asserts the Snoop Done
output to indicate that the snoop is done and the transaction can
continue.
4.4.8 Bus Errors
The BBCC signals Instruction bus errors synchronously to the
microprocessor so that the microprocessor will take an instruction bus
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