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參數(shù)資料
| 型號(hào)： | EV4101 |
| 廠商： | LSI Corporation |
| 英文描述： | 32-bit Microprocessor that Executes MIPS I,a Subset of MIPS II,and a Subset of the MIPS16 Instructions.(32位微處理器（執(zhí)行MIPS I,MIPS II的子集,MIPS16的子集指令）) |
| 中文描述： | 32位微處理器中執(zhí)行MIPS的我，一個(gè)子集的MIPS的第二，以及對(duì)MIPS16指令集。（32位微處理器（執(zhí)行MIPS的我，MIPS的二的子集，MIPS16的子集指令）） |
| 文件頁(yè)數(shù)： | 37/68頁(yè) |
| 文件大?。?/td> | 545K |
| 代理商： | EV4101 |
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TinyRISC
EV4101 Microprocessor Reference Device Technical Summary
37
6.1 Bus Interface Signals
AD[31:0]
Address/Data Bus
AD is the multiplexed address/data for the bus
transaction. This bus supplies the address during the first
clock of a bus transaction, and provides the data
thereafter.
Bidirectional
ASN
Address Strobe
ASN is active during the first clock cycle of every
transaction. A LOW on ASN indicates a valid address is
on AD[31:0].
Output
CBEN[3:0]
Command/Byte Enables
The Command/Byte enable signals carry command
information on the first cycle of a bus transaction and
carry byte enables during subsequent cycles. Valid
commands that the EV4101 drives on CBEN are Memory
Read (0b0110), Memory Write (0b0111), and Memory
Line Read (0b1110). Valid byte enables during reads and
writes are listed in the following table.
Bidirectional, im/xm=o/i
.
DEVSELN
Device Select
The PCI target asserts DEVSELN when it has
acknowledged that it is the slave for a particular
transaction. A bus error occurs if DEVSELN is not
asserted within six clock cycles of the assertion of
FRAMEN, resulting in an exception.
Bidirectional, im/xm=i/o
CBEN[3:0]
Transfer Type
0b
0000
0b
0001
0b
0011
0b
0111
0b
1000
0b
1011
0b
1100
0b
1101
0b
1110
Word
Tribyte
Halfword
Byte
Tribyte
Byte
Halfword
Byte
Byte
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