參數(shù)資料
型號: EV4101
廠商: LSI Corporation
英文描述: 32-bit Microprocessor that Executes MIPS I,a Subset of MIPS II,and a Subset of the MIPS16 Instructions.(32位微處理器(執(zhí)行MIPS I,MIPS II的子集,MIPS16的子集指令))
中文描述: 32位微處理器中執(zhí)行MIPS的我,一個子集的MIPS的第二,以及對MIPS16指令集。(32位微處理器(執(zhí)行MIPS的我,MIPS的二的子集,MIPS16的子集指令))
文件頁數(shù): 39/68頁
文件大?。?/td> 545K
代理商: EV4101
TinyRISC
EV4101 Microprocessor Reference Device Technical Summary
39
and monitors REQN to determine if an external DMA
device requires mastership of the bus. In Mode 2, the bus
arbiter is external to the EV4101, and the EV4101
asserts REQN when it needs to perform a transaction.
SDONEP
Snoop Done
The EV4101 asserts the Snoop Done signal when it has
completed its snoop. When a DMA transaction is being
performed on the bus, the target should monitor
SDONEP, and not assert TRDYN until SDONEP is HIGH.
SDONEP is generated asynchronously as the logical
combination of FRAMEN and CBEN[0].
Output
STOPN
Stop Bus Transaction
This signal is used in conjunction with TRDYN and
DEVSELN to inform the initiator to either abort the
transaction, retry the transaction, or stop the transaction.
The transaction is aborted when STOPN is asserted
and TRDYN and DEVSELN are both deasserted,
resulting in a bus error on the BBus.
The transaction is retried when STOPN and
DEVSELN are both asserted and TRDYN is
deasserted. The EV4101 usually retries the same
transaction after allowing other masters to acquire the
bus, if requested, but it is not guaranteed to do so.
The EV4101 has the option to prioritize its
transactions internally, so the initial transaction that
resulted in a retry may eventually be retried, but not
necessarily in the following cycle. Because a retry can
occur in the middle of a cache refill, the EV4101 will
not perform the transaction again, unless the
instruction/data is absolutely needed.
The transaction is stopped when STOPN, TRDYN,
and DEVSELN are deasserted. The target uses this
mechanism to tell the master that it cannot perform a
burst, or that it wants the current data transfer in the
burst to be the final data transfer. If the EV4101
interfaces to a PCI target that supports bursts, then
the target should issue a stop at the end of a burst
line, since the EV4101 address wraps and the PCI
target does not. STOPN remains asserted until
FRAMEN is HIGH.
Input
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