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參數(shù)資料
| 型號： | EV4101 |
| 廠商： | LSI Corporation |
| 英文描述： | 32-bit Microprocessor that Executes MIPS I,a Subset of MIPS II,and a Subset of the MIPS16 Instructions.(32位微處理器（執(zhí)行MIPS I,MIPS II的子集,MIPS16的子集指令）) |
| 中文描述： | 32位微處理器中執(zhí)行MIPS的我，一個子集的MIPS的第二，以及對MIPS16指令集。（32位微處理器（執(zhí)行MIPS的我，MIPS的二的子集，MIPS16的子集指令）） |
| 文件頁數(shù)： | 46/68頁 |
| 文件大小： | 545K |
| 代理商： | EV4101 |
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46
TinyRISC
EV4101 Microprocessor Reference Device Technical Summary
did not support bursts, it would have also asserted STOPN to indicate
that the first data transfer would be the last data transfer of the
transaction.
Clock Cycle 7 –
The EV4101 latches the data on the rising edge of
Clock Cycle 7. The target also deasserts TRDYN HIGH to indicate that
a wait state is needed before Word 2 is transferred.
Clock Cycle 8 –
The Initiator does not latch data, since TRDYN is
sampled as negated. TRDYN and AD are driven off of Clock Cycle 8, so
that the Initiator samples the data on Clock Cycle 9.
Clock Cycle 9 –
Word 2 is latched. Since FRAMEN is sampled LOW,
another transfer will occur.
Clock Cycle 10 –
Word 3 is latched. Since FRAMEN is sampled LOW,
another transfer will occur.
7.1.3 Transaction C: Single Word Read with FASTP Asserted
Clock Cycle 11 –
This example shows what will happen if the FASTP bit
of the SCR is set to one. Word 4 latched. Since FRAMEN is sampled
HIGH, this is the last word of the burst. At Clock Cycle 11, another
transaction begins. The complete transaction is not shown, since the only
interesting part is the potential bus contention at the edge of Clock
Cycle 11.
7.2 Single Word Writes and Burst Writes
Figure 5 shows Transaction A, a single word write, followed by
Transaction B, first and second words of a 2-word burst write, and
Transaction C, a single word write with wait state. A description of each
operation follows the figure.
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