- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362799 > EV4101 (LSI Corporation) 32-bit Microprocessor that Executes MIPS I,a Subset of MIPS II,and a Subset of the MIPS16 Instructions.(32位微處理器（執(zhí)行MIPS I,MIPS II的子集,MIPS16的子集指令）) PDF資料下載
參數(shù)資料
| 型號(hào)： | EV4101 |
| 廠商： | LSI Corporation |
| 英文描述： | 32-bit Microprocessor that Executes MIPS I,a Subset of MIPS II,and a Subset of the MIPS16 Instructions.(32位微處理器（執(zhí)行MIPS I,MIPS II的子集,MIPS16的子集指令）) |
| 中文描述： | 32位微處理器中執(zhí)行MIPS的我，一個(gè)子集的MIPS的第二，以及對(duì)MIPS16指令集。（32位微處理器（執(zhí)行MIPS的我，MIPS的二的子集，MIPS16的子集指令）） |
| 文件頁(yè)數(shù)： | 49/68頁(yè) |
| 文件大小： | 545K |
| 代理商： | EV4101 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)當(dāng)前第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)
TinyRISC
EV4101 Microprocessor Reference Device Technical Summary
49
7.2.4 Transaction C: Single Word Write with Wait State
Clock Cycle 8 –
Idle cycle. (If WBURSTN were deasserted at the rising
edge of Clock Cycle 8, and the next transaction was a write and on the
same page, a fast back-to-back transaction would have been performed.
As specified by the PCI specification, all targets must support fast back-
to-back writes.)
Clock Cycle 9 –
The write transaction begins.
Clock Cycle 10 –
The target asserts DEVSELN, indicating that it will
eventually respond. TRDYN is HIGH, creating a wait cycle.
Clock Cycle 11 –
TRDYN is deasserted. Data is transferred on the
rising edge of Clock Cycle 12.
8 Retry Support
A PCI target issues a retry to a transaction that it cannot fulfill by
asserting both STOPN and DEVSELN, while TRDYN remains
deasserted. To respond to a retry, the EV4101 relinquishes ownership of
the bus, allowing another PCI agent to become a master on the PCI bus
and perform a transaction. The EV4101 then requests ownership of the
bus, and either repeats the original transaction or performs a different
transaction. There is no guarantee that the original transaction will be
tried consecutively after a retry, because the EV4101 may have a
different transaction that has a higher priority by the time it reacquires
the bus.
If the retry is issued to the EV4101 during the middle of a Memory Line
Read, then the EV4101 may opt not to retry the transaction. This
situation occurs because a Memory Line Read is used to fill the cache
with additional instructions/data that may not have been implicitly
requested by EV4101. Note that the EV4101 option not to retry deviates
from the PCI protocol, which states that retries must be retried.
The PCI specification also describes a situation where a retry may be
issued in the middle of a burst transaction, when the target feels that it
is taking too long to fulfill the transaction (called the “slow target
disconnect”). This situation is not supported by the EV4101, and results
in a bus error, if attempted.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EV5103 | G5103 White LED Demo Board V1.0 |
| EV5103-10 | G5103 White LED Demo Board V1.0 |
| EV6001DN-00A | Monolithic Flyback/Forward DC-DC Converter Evaluation Board |
| EV6001DN-00D | WLED Driver Evaluation Board |
| EV7720DS-7782-00D | 150W Class D 5.1 Channel Audio Board |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EV4-1A | 制造商:MA-COM 制造商全稱:M/A-COM Technology Solutions, Inc. 功能描述:320 Vdc, 4 amp make/carry |
| EV42-100-11-SERIES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| EV42-100-12-SERIES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| EV42-100-21-SERIES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| EV42-100-22-SERIES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。