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參數(shù)資料
| 型號： | EVAL-AD1833AEB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 24-Bit, 192 kHz, DAC |
| 中文描述： | 24位，192千赫，數(shù)模轉(zhuǎn)換器 |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 687K |
| 代理商： | EVAL-AD1833AEB |
REV. 0
AD1833A
–13–
MCLK Select
The AD1833A allows the matching of available external MCLK
frequencies to the required internal MCLK rate. The MCLK
modification factor can be selected from 2, 1, or
2
/
3
by writing to
Bit 4 and Bit 3 of Control Register 3. Internally, the AD1833A
requires an MCLK of 24.576 MHz for sample rates of 48 kHz,
96 kHz, and 192 kHz. In the case of 48 kHz data with an
MCLK of 256 f
S
, a clock doubler is used, whereas with an
MCLK of 768 f
S
, a divide-by-3 block ( 3) is first implemented
followed by a clock doubler. With an MCLK of 512 f
S
, the
MCLK is passed through unmodified (see Table XII).
Table XII. MCLK Settings
Bit 4
Bit 3
Modification Factor
0
0
1
1
0
1
0
1
MCLK 2 Internally
MCLK 1 Internally
MCLK
2
/
3
Internally
Reserved
Channel Zero Status
The AD1833A provides individual logic output status indicators
when zero data is sent to a channel for 1024 or more consecutive
sample periods in all modes except right-justified. There is also
Table XIV. MCLK vs. Sample Rate Selection
Sampling Rate
f
S
(kHz)
32
64
128
Interpolator Mode
Required
Internal MCLK
Required (MHz)
Suitable External MCLK Frequencies (MHz)
MCLK 2
MCLK 1
MCLK
2
/
3
8
4
2
16.384
8192
16.384
24.576
44.1
88.2
176.4
8
4
2
22.5792
11.2896
22.5792
33.8688
48
96
192
8
4
2
24.576
12.288
24.576
36.864
Table XV. Volume Control Registers
Address
Reserved
*
Volume Control
15–12
11
10
9–0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
0
0
Channel 1 Volume Control (OUTL1)
Channel 2 Volume Control (OUTR1)
Channel 3 Volume Control (OUTL2)
Channel 4 Volume Control (OUTR2)
Channel 5 Volume Control (OUTL3)
Channel 6 Volume Control (OUTR3)
*
Must be programmed to zero.
a global zero flag that indicates all channels contain zero data.
The polarity of the zero signal is programmable by writing to
Control Bit 2 (see Table XIII). In right-justified mode, the six
individual channel flags are best used as three stereo zero flags
by combining pairs of them through suitable logic gates. Then,
when both the left and right inputs are zero for 1024 clock cycles,
i.e., a stereo zero input for 1024 sample periods, the combined
result of the two individual flags will become active, indicat-
ing a stereo zero.
Table XIII. Zero Detect
Bit 2
Channel Zero Status
0
1
Active High
Active Low
DAC Volume Control Registers
The AD1833A has six volume control registers, one for each of
the six DAC channels. Volume control is exercised by writing to
the relevant register associated with each DAC. This setting is
used to attenuate the DAC output. Full-scale setting (all 1s) is
equivalent to zero attenuation (see Table XV).
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| EVAL-AD1837AEB | 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk |
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