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| 型號(hào)： | EVAL-AD1838AEB |
| 廠(chǎng)商： | Analog Devices, Inc. |
| 元件分類(lèi)： | Codec |
| 英文描述： | 2 ADC, 6 DAC, 96KHZ 24 BIT CODEC |
| 中文描述： | 2的ADC，6 DAC的，96KHz的24位編解碼器 |
| 文件頁(yè)數(shù)： | 17/24頁(yè) |
| 文件大?。?/td> | 531K |
| 代理商： | EVAL-AD1838AEB |
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REV. A
AD1838A
–17–
Table IV. Pin Function Changes in Auxiliary Mode
Pin Name
I
2
S Mode
I
2
S Data Out, Internal ADC
I
2
S Data In, Internal DAC1
I
2
S Data In, Internal DAC2
I
2
S Data In, Internal DAC3
Not Connected
LRCLK for ADC
BCLK for ADC
LRCLK In/Out Internal DACs
Auxiliary Mode
ASDATA (O)
DSDATA1 (I)
DSDATA2 (I)/AAUXDATA1 (I)
DSDATA3 (I)/AAUXDATA2 (I)
AAUXDATA3 (I)
ALRCLK (O)
ABCLK (O)
DLRCLK (I)/AUXLRCLK (I/O)
TDM Data Out to SHARC.
TDM Data In from SHARC.
AUX-I
2
S Data In 1 (from External ADC).
AUX-I
2
S Data In 2 (from External ADC).
AUX-I
2
S Data In 3 (from External ADC).
TDM Frame Sync Out to SHARC (FSTDM).
TDM BCLK Out to SHARC.
AUX LRCLK In/Out. Driven by external LRCLK
from ADC in slave mode. In master mode,
driven by MCLK/512.
AUX BCLK In/Out. Driven by external BCLK from
ADC in slave mode. In master mode, driven by
MCLK/8.
AUX-I
2
S Data Out (to External DAC).
DBCLK (I)/AUXBCLK (I/O)
BCLK In/Out Internal DACs
DAUXDATA (O)
Not Connected
FSTDM
INTERNAL
ADC L1
AUX_ADC L2
AUX_ADC L3
AUX_ADC L4
INTERNAL
ADC R1
AUX_ADC R2
AUX_ADC R3
AUX_ADC R4
INTERNAL
DAC L1
INTERNAL
DAC L2
INTERNAL
DAC L3
INTERNAL
DAC R1
INTERNAL
DAC R2
INTERNAL
DAC R3
MSB TDM
CH
LEFT
RIGHT
I
2
S – MSB RIGHT
I
2
S – MSB LEFT
BCLK
TDM
ASDATA1
TDM (OUT)
ASDATA
DSDATA1
TDM (IN)
DSDATA1
AUX
LRCLK I
S
(FROM AUX ADC NO. 1)
AUX
BCLK I
2
S
(FROM AUX ADC NO. 1)
AAUXDATA1 (IN)
(FROM AUX ADC NO. 1)
AAUXDATA2 (IN)
(FROM AUX ADC NO. 2)
AAUXDATA3 (IN)
(FROM AUX ADC NO. 3)
AUXBCLK FREQUENCY IS 64
FRAME RATE; TDM BCLK FREQUENCY IS 256
FRAME RATE.
T
A
2
S
MSB TDM
CH
32
32
MSB TDM
CH
MSB TDM
CH
I
2
S – MSB RIGHT
I
2
S – MSB LEFT
I
2
S – MSB RIGHT
I
2
S – MSB LEFT
INTERNAL
DAC L4
INTERNAL
DAC R4
Figure 11. Auxiliary Mode Timing
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