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參數(shù)資料
| 型號： | EVAL-AD1852EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 24-Bit Stereo DAC Evaluation Board |
| 中文描述： | 24位立體聲DAC評估板 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 486K |
| 代理商： | EVAL-AD1852EB |
REV. 0
EVAL-AD1852EB
–7–
// LabView selection 6, RJ_16, 16-Bit
RJ_16 = ( XMODC & ( QM3 & QM2 & QM1 & QM0) );
“=============================================================================
EQUATIONS
// Registers holding streaming mode codes from CPU’s LabView control program.
[QM3, QM2, QM1, QM0] := [QM2, QM1, QM0, MODSTM];
[QM3, QM2, QM1, QM0].clk = MODCLK;
// AD1852 DAC Interface Mode Select
IDPM0 = !XMODC & (I2S # DSP);
IDPM1 = !XMODC & (LJ # DSP);
// CS8414 DIR Interface Mode Select
M0 = !RJ_16;
M1 = !I2S;
M2 = !(DSP # RJ_16);
// External I/O Data Port Output Enabled by SPDIF_EXT
ESDATA.oe = SPDIF_EXT;
ELRCLK.oe = SPDIF_EXT;
EBCLK.oe = SPDIF_EXT;
ESDATA = SPDIF_EXT & SDATA;
ELRCLK = SPDIF_EXT & LRCLK;
EBCLK = SPDIF_EXT & BCLK;
// Shift register for DSP, RJ_20, and RJ_24 modes
[QL, QK, QJ, QI, QH, QG, QF, QE, QD, QC, QB, QA] := [QK, QJ, QI,
QH, QG, QF, QE, QD, QC, QB, QA, ISDATA];
[Q24, Q20] := [QH, QL];
QDSP := QA;
[QL, QK, QJ, QI, QH, QG, QF, QE, QD, QC, QB, QA].clk = !IBCLK;
[Q24, Q20].clk = IBCLK;
QDSP.clk = IBCLK;
// AD1852 DAC DAU Signals
SDATA = SPDIF_EXT &(ISDATA &(LJ # I2S # RJ_16)
# DSP & QDSP # RJ_20 & Q20 # RJ_24 & Q24) # !SPDIF_EXT & ESDATA;
LRCLK = SPDIF_EXT & ILRCLK # !SPDIF_EXT & ELRCLK;
BCLK = SPDIF_EXT & ((LJ # RJ_20 # RJ_24) & !IBCLK
# (I2S # DSP # RJ_16) & IBCLK) # !SPDIF_EXT & EBCLK;
MCLK = SPDIF_EXT & IMCLK
# !SPDIF_EXT & EMCLK;
// DAC Deemphasis Control Signal
DEEMPH = !NPREEMPH # !NDEEMPH;
// Slave MCLK for SPI output port
MCLKO = !MCLK;
// LED Status Driver Outputs - LED lights when output low
NLVERF = !VERF;
NLZL = !ZL;
NLZR = !ZR;
NLDEEMPH = !DEEMPH;
“==============================================================================
END IF_Logic
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