參數(shù)資料
型號(hào)： EVAL-AD1870EB
廠商： Analog Devices, Inc.
英文描述： Single-Supply 16-Bit Stereo ADC
中文描述： 單電源16位立體聲ADC
文件頁(yè)數(shù)： 11/20頁(yè)
文件大小： 283K
代理商： EVAL-AD1870EB
AD1870
REV. A
–
11
–
Figure 5 shows a circuit for obtaining a 3 dB improvement in
dynamic range by using both channels of a single AD1870 with a
mono input. A stereo implementation would require using
two AD1870s and using the recommended input structure
shown in Figure 2. Note that a single microprocessor would likely
be able to handle the averaging requirements for both left and
right channels.
AD1870
RECOMMENDED
INPUT BUFFER
SINGLE
CHANNEL
INPUT
DIGITAL
AVERAGER
AD1870
V
IN
R
V
IN
L
SINGLE
CHANNEL
OUTPUT
Figure 5. Increasing Dynamic Range By Using Two
AD1870 Channels
DIGITAL INTERFACE
Modes of Operation
The AD1870
’
s flexible serial output port produces data in
two
’
s-complement, MSB-first format. The input and output
signals are TTL logic-level compatible. Time multiplexed serial
data is output on SOUT (Pin 26), left channel then right chan-
nel, as determined by the left/right clock signal L
R
CK (Pin 1).
Note that there is no method for forcing the right channel to
precede the left channel. The port is configured by pin selections.
The AD1870 can operate in either Master or Slave Mode, with
the data in right-justified, I
2
S compatible, word clock controlled,
or left-justified positions.
The various mode options are pin programmed with the S/
M
(Slave/
Master
) Pin (7), the Right/
Left
Justify Pin (21), and the
MSBDLY
Pin (22). The function of these pins is summarized
below.
S/
M
R
L
JUST
MSBDLY
WCLK
BCLK
L
R
CK
Serial Port Operation Mode
1
1
1
Output
Input
Input
Slave Mode. WCLK frames the data. The MSB is output on the
17th BCLK cycle. Provides right-justified data in slave mode
with a 64
×
f
S
BCLK frequency. See Figure 7.
Slave Mode. The MSB is output in the BCLK cycle after
WCLK is detected HI. WCLK is sampled on the BCLK active
edge, with the MSB valid on the next BCLK active edge. Tying
WCLK HI results in I
2
S-justified data. See Figure 8.
1
1
0
Input
Input
Input
1
0
1
Output
Input
Input
Slave Mode. Data left-justified with WCLK framing the data.
WCLK rises immediately after an L
R
CK transition. The MSB is
valid on the first BCLK active edge. See Figure 9.
Slave Mode. Data I
2
S-justified with WCLK framing the data.
WCLK rises in the second BCLK cycle after an L
R
CK transi-
tion. The MSB is valid on the second BCLK active edge. See
Figure 10.
1
0
0
Output
Input
Input
0
1
1
Output
Output
Output
Master Mode. Data right-justified. WCLK frames the data,
going HI in the 17th BCLK cycle. BCLK frequency = 64
×
f
S
.
See Figure 11.
0
1
0
Output
Output
Output
Master Mode. Data right-justified + 1. WCLK is pulsed in the
17th BCLK cycle, staying HI for only 1 BCLK cycle. BCLK
frequency = 64
×
f
S
. See Figure 12.
Master Mode. Data left-justified. WCLK frames the data.
BCLK frequency = 64
×
f
S
. See Figure 13.
Master Mode. Data I
2
S-justified. WCLK frames the data.
BCLK frequency = 64
×
f
S
. See Figure 14.
0
0
1
Output
Output
Output
0
0
0
Output
Output
Output
相關(guān)PDF資料
PDF描述
EVAL-AD1896EB Automotive Low-Cost Non-Volatile FPGA Family; Voltage: 1.2V; Grade: -5; Package: Lead-Free ftBGA; Pins: 256; Temperature: AUTO; LUTs (k): 8
EVAL-AD1928EBZ 2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec
EVAL-AD1928EB 2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec
EVAL-AD1938EB 4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC
EVAL-AD1939EB 4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EVAL-AD1871EB 制造商:Analog Devices 功能描述:STEREO AUD, 24BIT, 96 KHZ, MULTIBIT- ADC - Bulk
EVAL-AD1871EBZ 功能描述:BOARD EVAL FOR AD1871 RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:* 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件
EVAL-AD1895EB 制造商:Analog Devices 功能描述:EVAL BD FOR AD1895 192KHZ 8:1 STEREO - Bulk
EVAL-AD1896EB 制造商:Analog Devices 功能描述:Evaluation Kit For 24-Bit, High-Performance, Single-Chip, Second Generation Asynchronous Sample Rate Converter 制造商:Analog Devices 功能描述:EVAL KIT FOR AD1896 7.75:1 TO 1:8, 192KHZ STEREO ASRC EVAL B - Bulk
EVAL-AD1928EB 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*