參數(shù)資料
型號： EVAL-AD1896EB
廠商： Analog Devices, Inc.
英文描述： Automotive Low-Cost Non-Volatile FPGA Family; Voltage: 1.2V; Grade: -5; Package: Lead-Free ftBGA; Pins: 256; Temperature: AUTO; LUTs (k): 8
中文描述： AD1896 7.75:1到1:8，192千赫立體聲ASRC評估板
文件頁數(shù)： 21/28頁
文件大?。?/td> 549K
代理商： EVAL-AD1896EB
REV. 0
EVAL-AD1896EB
–21–
I_SDATA, ISCLK, ILRCLK
node istype 'com';
//================================================================================
in_pld.abl
"MACROS
//INPUT SERIAL DATA FORMATS
// S3 position 0, LEFT-JUSTIFIED
LJ = ( IN_MODE2 & IN_MODE1 & IN_MODE0);
// S3 position 1, I2S
I2S = ( IN_MODE2 & IN_MODE1 & !IN_MODE0);
// S3 position 2, RIGHT-JUSTIFIED 24-BITS
RJ24 = ( IN_MODE2 & !IN_MODE1 & IN_MODE0);
// S3 position 3, RIGHT-JUSTIFIED 20-BITS
RJ20 = ( IN_MODE2 & !IN_MODE1 & !IN_MODE0);
// S3 position 4, RIGHT-JUSTIFIED 18-BITS
RJ18 = ( !IN_MODE2 & IN_MODE1 & IN_MODE0);
// S3 position 5, RIGHT-JUSTIFIED 16-BITS
RJ16 = ( !IN_MODE2 & IN_MODE1 & !IN_MODE0);
// S3 positons 6,7 are not used
//MASTER_SLAVE MODE MAPPING
// S4 position 7, INPUT/OUTPUT SERIAL PORTS IN SLAVE MODE
BOTH_SLAVE = (!MS_MODE2 & !MS_MODE1 & !MS_MODE0);
// S4 position 6, OUTPUT SERIAL PORT IN MASTER MODE FSX768
O_MAS_768 = (!MS_MODE2 & !MS_MODE1 & MS_MODE0);
// S4 position 5, OUTPUT SERIAL PORT IN MASTER MODE FSX512
O_MAS_512 = (!MS_MODE2 & MS_MODE1 & !MS_MODE0);
// S4 position 4, OUTPUT SERIAL PORT IN MASTER MODE FSX256
O_MAS_256 = (!MS_MODE2 & MS_MODE1 & MS_MODE0);
// S4 position 3, INPUT SERIAL PORT IN MATCHED_PHASE MODE
MATCH_PHASE = (MS_MODE2 & !MS_MODE1 & !MS_MODE0);
// S4 position 2, INPUT SERIAL PORT IN MASTER MODE FSX768
IN_MAS_768 = (MS_MODE2 & !MS_MODE1 & MS_MODE0);
// S4 position 1, INPUT SERIAL PORT IN MASTER MODE FSX512
IN_MAS_512 = (MS_MODE2 & MS_MODE1 & !MS_MODE0);
// S4 position 0, INPUT SERIAL PORT IN MASTER MODE FSX256
IN_MAS_256 = (MS_MODE2 & MS_MODE1 & MS_MODE0);
"==========================================================================
EQUATIONS
// AD1896 ASRC Input Serial Port Interface Mode Select
SMODE_I_2 = RJ24 # RJ20 # RJ18 # RJ16;
SMODE_I_1 = RJ24 # RJ20;
SMODE_I_0 = RJ24 # RJ18 # I2S;
// CS8414 DIR Interface Mode Select, DIR_FSYNC and DIR_SCLK are bi-directional signals.
// If AD1896 input serial port is in slave mode, the CS8414 DIR RJ-24 and RJ-20 modes
// are not supported.
M0 = (RJ16 & (BOTH_SLAVE # MATCH_PHASE # O_MAS_768 # O_MAS_512 # O_MAS_256))
# ((LJ # RJ24 # RJ20 # I2S) & (IN_MAS_768 # IN_MAS_512 # IN_MAS_256));
M1 = ((I2S # RJ18) & (BOTH_SLAVE # MATCH_PHASE # O_MAS_768 # O_MAS_512 # O_MAS_256))
# (I2S & (IN_MAS_768 # IN_MAS_512 # IN_MAS_256));
M2 = RJ18 # RJ16;
M3 = 0;
相關(guān)PDF資料
PDF描述
EVAL-AD1928EBZ 2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec
EVAL-AD1928EB 2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec
EVAL-AD1938EB 4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC
EVAL-AD1939EB 4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC
EVAL-AD1935EB 4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EVAL-AD1928EB 制造商:AD 制造商全稱:Analog Devices 功能描述:2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec
EVAL-AD1928EBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec
EVAL-AD1934EB 制造商:AD 制造商全稱:Analog Devices 功能描述:8-Channel DAC with PLL, 192 kHz, 24 Bits
EVAL-AD1935EB 制造商:AD 制造商全稱:Analog Devices 功能描述:4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC
EVAL-AD1936EB 制造商:AD 制造商全稱:Analog Devices 功能描述:4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC
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