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參數(shù)資料
| 型號： | EVAL-AD1896EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Automotive Low-Cost Non-Volatile FPGA Family; Voltage: 1.2V; Grade: -5; Package: Lead-Free ftBGA; Pins: 256; Temperature: AUTO; LUTs (k): 8 |
| 中文描述： | AD1896 7.75:1到1:8，192千赫立體聲ASRC評估板 |
| 文件頁數(shù)： | 4/28頁 |
| 文件大?。?/td> | 549K |
| 代理商： | EVAL-AD1896EB |
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REV. 0
EVAL-AD1896EB
–4–
Table III. Master/Slave Mode Configuration
Switch
SW4
Input Header (HDR3)
SCLK_I
Output Header (HDR5)
SCLK_O
MCLK_I
[MHz]
Jumper
JP4 Short
f
S_IN
132.3 kHz
66.15 kHz
44.1 kHz
Not Used
Set Externally
Set Externally
Set Externally
Set Externally
f
S_OUT
Set Externally
Set Externally
Set Externally
Not Used
132.3 kHz
66.15 kHz
44.1 kHz
Set Externally
LRCLK_I
LRCLK_O
0
1
2
3
4
5
6
7
Output
Output
Output
Input
Input
Input
Input
Input
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Input
Input
Input
Input
Input
Output
Output
Output
Input
33.8688
33.8688
33.8688
33.8688
33.8688
33.8688
33.8688
33.8688
2-3
2-3
2-3
2-3
2-3
2-3
2-3
2-3
Table IV. Input Interface Formats
SMODE_IN_[2:0]
2
1
S3 Switch Position
0
Input Interface Format
0
1
2
3
4
5
6
7
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
1
1
0
1
0
0
1
Left Justified
I
2
S
Right Justified, 24 Bits
Right Justified, 20 Bits
Right Justified, 18 Bits
Right Justified, 16 Bits
Not Used
Not Used
DIGITAL AUDIO OUTPUT SIGNALS
Similar to the input serial port, output serial data (SDATA_O,
SCLK_O, and LRCLK_O signals) can be accessed in three
different ways using this evaluation board.
1. Refer to Figure 8. Direct digital output header (HDR5) or,
alternatively, TDM_OUT header (HDR2) can be used to
monitor the output serial data of the AD1896 (SDATA_O
signal) in the digital form. HDR5 provides LRCLK_O,
SCLK_O, and SDATA_O in 3-wire interface format;
whereas, HDR2 should be used in TDM mode to interface
the TDM output data to the SHARC DSP board.
2. SPDIF output through connector J2, which is generated by
the SPDIF transmitter CS8404. In this case, SCLK_O,
LRCLK_O, and SDATA_O from AD1896 are encoded in
the SPDIF signal. Similar to the SPDIF receiver, the output
sample rates above 96 kHz are not possible due to the
transmitter functionality.
Note that SPDIF output is supported
only for the output port in 768
256
f
S_OUT
master mode (Switch S4 positions 4, 5, 6).
3. RCA jack J6 and J7 provide stereo LEFT and RIGHT analog
output signals from AD1852 DAC. Refer to Figure 10.
Interpolation ratio of the DAC needs to be set based on the
sample rate and set by jumper JP2.
DAC analog output is
supported only when the AD1896 output port is configured in
768
f
S_OUT
, 512
f
S_OUT
, and 256
(Switch S4 positions 4, 5, 6).
SCLK_O and LRCLK_O signals of output serial port are
bidirectional signals. Logic levels on pins MMODE_ [2:0]
f
S_OUT
, 512
f
S_OUT
, and
f
S_OUT
master mode
control the direction of these signals. Please refer to Table II
for the switch position S4 setting to control the Master/Slave
mode of the output serial port. The output interface mode,
such as I
2
S, LJ, RJ, and TDM mode, is set by the pins
SMODE_OUT_[2:0]. Also, the output port has two more pins
WLNGTH_OUT_[1:0] to set the output word width to 24, 20,
18, or 16 bits. The logic levels on SMODE_OUT_ [1:0] and
WLNGTH_OUT_ [1:0] pins allow different serial output data
formats. As shown in Tables V and VI, set the jumpers one and
two of JP1 for the word width and three and four of JP1 for the
output data format.
Table V. Output Interface Formats
SMODE_OUT_[1:0]
JP1[4:3]
1
0
Interface Format
00
01
10
11
0
0
1
1
0
1
0
1
Left-Justified (LJ)
I
2
S
TDM Mode
Right-Justified (RJ)
Table VI. Output Signal Word Width
WLNGTH_OUT_[1:0]
JP1[2:1]
1
0
Word
00
01
10
11
0
0
1
1
0
1
0
1
24 Bits
20 Bits
18 Bits
16 Bits
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| EVAL-AD1928EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec |
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