參數(shù)資料
型號(hào)： EVAL-AD1896EB
廠商： Analog Devices, Inc.
英文描述： Automotive Low-Cost Non-Volatile FPGA Family; Voltage: 1.2V; Grade: -5; Package: Lead-Free ftBGA; Pins: 256; Temperature: AUTO; LUTs (k): 8
中文描述： AD1896 7.75:1到1:8，192千赫立體聲ASRC評(píng)估板
文件頁(yè)數(shù)： 6/28頁(yè)
文件大?。?/td> 549K
代理商： EVAL-AD1896EB
REV. 0
EVAL-AD1896EB
–6–
DEFAULT SETUP
SCLK
LRCLK
SDATA
SCLK_O
LRCLK_O
SDATA_O
SCLK_I
LRCLK_I
SDATA_I
SCLK
LRCLK
SDATA
AD1896
U13
MCLK_O
MCLK_I
INPUT DATA:
DIRECT DIGITAL INPUT HEADER
HDR3 (DDI)
f
S_IN
SET EXTERNALLY
f
S_OUT
44.1kHz
1
2 3
JUMPER JP4
33.868MHz CRYSTAL
OUTPUT DATA:
DIRECT DIGITAL OUTPUT HEADER
HDR5 (DDO)
AD1852 DAC
U12
SCLK_I
LRCLK_I
SDATA_I
MCLK_I
LEFT OUT
RIGHT OUT
CS8404 DIT
U6
SPDIF OUTPUT
128
f
S
256f
S
MCLK_I
SCLK_I
LRCLK_I
SDATA_I
CLOCK DIVIDER
256
f
S
128
f
S
Figure 3. Default Setup (Refer to Figure 5 for Detailed Setup)
Table IX. MCLK_I Frequencies for Common Sample Rates in Master Mode
MCLK_I Frequency (MHz)
512
f
S
11.289600
12.288000
24.576000
Sample Rate (kHz)
256
f
S
768
f
S
33.868800
44.100
48.000
96.000
22.579200
24.576000
EXTERNAL 192 kHz CLOCK GENERATOR CIRCUIT
An external circuit can be used to generate the 192 kHz clock
signals (SCLK, LRCLK) using on-board 128
f
S
clock oscilla-
tor (U15) running at 24.576 MHz. Please refer to Figure 4 for
the schematic and instructions on how to connect the exter-
nal circuit to the AD1896EB. In general, external SCLK and
LRCLK can be used for converting the audio input data to 192 kHz
rate by connecting SCLK to SCLK_O (DDO_SCLK_O,
HDR5 on the AD1896EB) and LRCLK to LRCLK_O
(DDO_LRCLK_O, HDR5 on the AD1896EB). On-board SPDIF
transmitter CS8404 (U6) does not support sample rates above
96 kHz.
ATTACHMENTS
Appendix A
1. External 192 kHz Clock Generator Circuit
2. AD1896 Evaluation Board Block Diagram, Schematics, and
Layout Plots
3. Bill of Materials
4. PLD Code
FURTHER INFORMATION
Ordering Information
Order number is EVAL-AD1896EB
For Application Questions or Technical Support
Contact Analog Devices’ Central Applications Department at
1-781-937-1428 for assistance.
TYPICAL PERFORMANCE
Typical performance of the AD1896 for 44.1 kHz:48 kHz (asynchronous) sample rate is listed below.
1. DNR, No Filter
–139 dBFS, 20 Hz to 20 kHz (–60 dBFS)
2. DNR, A-Weighted
–142 dBFS, 20 Hz to 20 kHz (–60 dBFS)
3. THD+N, No Filter
–120 dBFS, 20 Hz to 20 kHz (0 dBFS)
4. Frequency Response
±
0.015 dB, 20 Hz to 20 kHz (0 dBFS)
相關(guān)PDF資料
PDF描述
EVAL-AD1928EBZ 2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec
EVAL-AD1928EB 2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec
EVAL-AD1938EB 4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC
EVAL-AD1939EB 4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC
EVAL-AD1935EB 4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EVAL-AD1928EB 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec
EVAL-AD1928EBZ 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec
EVAL-AD1934EB 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:8-Channel DAC with PLL, 192 kHz, 24 Bits
EVAL-AD1935EB 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC
EVAL-AD1936EB 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC
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