參數(shù)資料
型號(hào)： EVAL-AD1928EB
廠(chǎng)商： Analog Devices, Inc.
元件分類(lèi)： Codec
英文描述： 2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec
中文描述： 2藝發(fā)局/ 8鎖相環(huán)，192千赫，24位編解碼器數(shù)模轉(zhuǎn)換器
文件頁(yè)數(shù)： 19/32頁(yè)
文件大?。?/td> 354K
代理商： EVAL-AD1928EB
AD1928
DAISY-CHAIN MODE
The AD1928 also allows a daisy-chain configuration to expand
the system to 4 ADCs and 16 DACs (see Figure 18). In this mode,
the DBCLK frequency is 512 f
S
. The first eight slots of the DAC
TDM data stream belong to the first AD1928 in the chain and
the last eight slots belong to the second AD1928. The second
AD1928 is the device attached to the DSP TDM port.
To accommodate 16 channels at a 96 kHz sample rate, the
AD1928 can be configured into a dual-line TDM mode, as
shown in Figure 19. This mode allows a slower DBCLK than
normally required by the one-line TDM mode.
Again, the first four channels of each TDM input belong to the
first AD1928 in the chain and the last four channels belong to
the second AD1928.
The dual-line TDM mode can also be used to send data at a
192 kHz sample rate into the AD1928, as shown in Figure 20.
Rev. 0 | Page 19 of 32
There are two configurations for the ADC port to work in
daisy-chain mode. The first one is with an ABCLK at 256 f
S
,
shown in Figure 21. The second configuration is shown in
Figure 22. Note that in the 512 f
S
ABCLK mode, the ADC
channels occupy the first eight slots; the second eight slots are
empty. The TDM_IN of the first AD1928 must be grounded in
all modes of operation.
The input/output pins of the serial ports are defined according
to the serial mode selected. See Table 13 for a detailed
description of the function of each pin. See Figure 26 for a
typical AD1928 configuration with two external stereo DACs
and two external stereo ADCs.
Figure 23 through Figure 25 show the serial mode formats. For
maximum flexibility, the polarity of LRCLK and BCLK are
programmable. In these figures, all of the clocks are shown with
their normal polarity. The default mode is I
2
S.
DLRCLK
DBCLK
8 DAC CHANNELS OF THE FIRST IC IN THE CHAIN
8 UNUSED SLOTS
8 DAC CHANNELS OF THE SECOND IC IN THE CHAIN
MSB
DSDATA1 (TDM_IN)
OF THE SECOND AD1928
DSDATA2 (TDM_OUT)
OF THE SECOND AD1928
THIS IS THE TDM
TO THE FIRST AD1928
DAC L1
DAC R1
DAC L2
DAC R2
DAC L3
DAC R3
DAC L4
DAC R4
DAC L1
DAC R1
DAC L2
DAC R2
DAC L3
DAC R3
DAC L4
DAC R4
DAC L1
DAC R1
DAC L2
DAC R2
DAC L3
DAC R3
DAC L4
DAC R4
32 BITS
DSP
SECOND
AD1928
FIRST
AD1928
0
Figure 18. Single-Line DAC TDM Daisy-Chain Mode (Applicable to 48 kHz Sample Rate, 16-Channel, Two-AD1928 Daisy Chain)
相關(guān)PDF資料
PDF描述
EVAL-AD1938EB 4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC
EVAL-AD1939EB 4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC
EVAL-AD1935EB 4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC
EVAL-AD1936EB 4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC
EVAL-AD1937EB 4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EVAL-AD1928EBZ 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec
EVAL-AD1934EB 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:8-Channel DAC with PLL, 192 kHz, 24 Bits
EVAL-AD1935EB 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC
EVAL-AD1936EB 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC
EVAL-AD1937AZ 功能描述:BOARD EVAL FOR AD1937 RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源
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