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參數(shù)資料
| 型號(hào)： | EVAL-AD1928EBZ |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | Codec |
| 英文描述： | 2 ADC/8 DAC with PLL, 192 kHz, 24-Bit Codec |
| 中文描述： | 2藝發(fā)局/ 8鎖相環(huán)，192千赫，24位編解碼器數(shù)模轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 24/32頁(yè) |
| 文件大?。?/td> | 354K |
| 代理商： | EVAL-AD1928EBZ |
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AD1928
CONTROL REGISTERS
DEFINITIONS
The format is the same for I
2
C and SPI ports. The global address for the AD1928 is 0x04, shifted left one bit due to the R/W bit. All
registers are reset to 0, except for the DAC volume registers that are set to full volume. Note that the first setting in each control register
parameter is the default setting.
Rev. 0 | Page 24 of 32
Table 14. Register Format
Global Address
Bit
23:17
R/W
16
Register Address
15:8
Data
7:0
Table 15. Register Addresses and Functions
Address
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Function
PLL and Clock Control 0
PLL and Clock Control 1
DAC Control 0
DAC Control 1
DAC Control 2
DAC individual channel mutes
DAC 1L volume control
DAC 1R volume control
DAC 2L volume control
DAC 2R volume control
DAC 3L volume control
DAC 3R volume control
DAC 4L volume control
DAC 4R volume control
ADC Control 0
ADC Control 1
ADC Control 2
PLL AND CLOCK CONTROL REGISTERS
Table 16. PLL and Clock Control 0 Register
Bit
Value
0
0
1
2:1
00
01
10
11
4:3
00
01
10
11
6:5
00
01
10
11
7
0
1
Function
Normal operation
Power-down
Input 256 (×44.1 kHz or 48 kHz)
Input 384 (×44.1 kHz or 48 kHz)
Input 512 (×44.1 kHz or 48 kHz)
Input 768 (×44.1 kHz or 48 kHz)
XTAL oscillator enabled
256 × f
S
VCO output
512 × f
S
VCO output
Off
MCLKI/XI
DLRCLK
ALRCLK
Reserved
Disable: ADC and DAC idle
Enable: ADC and DAC active
Description
PLL power-down
MCLKI/XI pin functionality (PLL active), master clock rate setting
MCLKO/XO pin, master clock rate setting
PLL input
Internal master clock enable
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