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參數(shù)資料
| 型號： | EVAL-AD1935EB |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | Codec |
| 英文描述： | 4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC |
| 中文描述： | 4模數(shù)轉(zhuǎn)換器/ 8鎖相環(huán)，192千赫，24位編解碼器數(shù)模轉(zhuǎn)換器 |
| 文件頁數(shù)： | 12/30頁 |
| 文件大?。?/td> | 376K |
| 代理商： | EVAL-AD1935EB |
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AD1935/AD1936/AD1937/AD1938/AD1939
Preliminary Technical Data
Serial Data Ports—Data Format
Rev. Pr
I
| Page 12 of 30
The eight DAC channels output or accept a common serial bit clock
and left-right framing clock to clock in the serial data. The four
ADC channels output or accept a common serial bit clock and left-
right framing clock to clock out the data. The clock signals are all
synchronous with the sample rate. In the AUX Modes, set in ADC
Control 1 and DAC Control 0, the DACs use the ADC serial bit
clock and left-right clock as the DAC clock pins are used for the
auxiliary ADC/DAC serial clocks.
The ADC and DAC serial data modes default to I
2
S. The ports can
also be programmed for left-justified, right-justified and TDM
modes. The word width is 24 bits by default and can be
programmed for 16 or 20 bits. The normal TDM mode can be
daisy-chained with a second AD193X and will support 16 channels
at 48 kHz, 8 channels at 96 kHz or 4 channels at 192 kHz. There is
also a dual-line TDM mode to support 8 channels at 192 kHz.
The special auxiliary modes are provided to allow two external
stereo ADCs and/or two external stereo DACs to be interfaced with
the AD193X to provide up to 8 in/12 out operation or 2 AD193Xs
to be chained for up to 16 in/16 out operation. These modes
provide a glueless interface to a single SHARC serial port, allowing
the DSP to access up to 16 channels of analog I/O. In these modes
many pins are redefined, see table 10. See Figure 18 for details of
these modes.
The following figures show the serial mode formats.
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
LRCLK
BCLK
SDATA
LEFT CHANNEL
RIGHT CHANNEL
LEFT CHANNEL
RIGHT CHANNEL
MSB
LSB
LSB
LSB
LSB
LSB
LEFT JUSTIFIED MODE––16 BITS TO 24 BITS PER CHANNEL
I
2
S MODE––16 BITS TO 24 BITS PER CHANNEL
RIGHT JUSTIFIED MODE––SELECT NUMBER OF BITS PER CHANNEL
DSP MODE––16 BITS TO 24 BITS PER CHANNEL
NOTES
1. DSP MODE DOES NOT IDENTIFY CHANNEL
2. LRCLK NORMALLY OPERATES AT f
S
EXCEPT FOR DSP MODE WHICH IS 2
×
f
3. BCLK FREQUENCY IS NORMALLY 64
×
LRCLK BUT MAY BE OPERATED IN BURST MODE
MSB
MSB
MSB
LSB
LEFT CHANNEL
MSB
LSB
MSB
RIGHT CHANNEL
LSB
MSB
MSB
1/f
S
Figure 13. Stereo Serial Modes
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD1936EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC |
| EVAL-AD1937AZ | 功能描述:BOARD EVAL FOR AD1937 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| EVAL-AD1937EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC |
| EVAL-AD1937EBZ | 制造商:Analog Devices 功能描述:EB SINGLE CHIP CODEC 4 ADC'S W/DIFF OUTP - Boxed Product (Development Kits) |
| EVAL-AD1938AZ | 功能描述:BOARD EVAL FOR AD1938 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
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