參數(shù)資料
型號: EVAL-AD1937EB
廠商: Analog Devices, Inc.
元件分類: Codec
英文描述: 4 ADC/8 DAC with PLL, 192 kHz, 24 Bit CODEC
中文描述: 4模數(shù)轉(zhuǎn)換器/ 8鎖相環(huán),192千赫,24位編解碼器數(shù)模轉(zhuǎn)換器
文件頁數(shù): 18/30頁
文件大?。?/td> 376K
代理商: EVAL-AD1937EB
AD1935/AD1936/AD1937/AD1938/AD1939
Preliminary Technical Data
Pin No.
52
53
54
55
56
57
58
59
60
61
62
63
64
Rev. Pr
I
| Page 18 of 30
In/Out
O
I
I
I
I
I
I
I
I
O
I
Mnemonic
CM
ADC1LP
ADC1LN
ADC1RP
ADC1RN
ADC2LP
ADC2LN
ADC2RP
ADC2RN
LF
AVDD
Description
Common Mode Reference Filter Capacitor Connection. Bypass with 10 μF||100 nF to AGND.
ADC1 Left Positive Input.
ADC1 Left Negative Input.
ADC1 Right Positive Input.
ADC1 Right Negative Input.
ADC2 Left Positive Input.
ADC2 Left Negative Input.
ADC2 Right Positive Input.
ADC2 Right Negative Input.
PLL Loop Filter, Return to AVDD.
Analog Power Supply. Connect to analog 3.3 V supply.
No Connect.
No Connect.
Table 14. Pin Function Description—64-Lead LQFP (AD1937, AD1939)
64-Lead LQFP Plastic Package – AD1935
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
In/Out
I
I
I
I
I
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I/O
I/O
O
O
I/O
I/O
I
I/O
I
I
I
I
Mnemonic
AGND
MCLKI/XI
MCLK/XO
AGND
AVDD
OL3
OR3
OL4
OR4
PD/RST
DSDATA4
DGND
DVDD
DSDATA3
DSDATA2
DSDATA1
DBCLK
DLRCLK
VSUPPLY
VSENSE
VDRIVE
ASDATA2
ASDATA1
ABCLK
ALRCLK
CIN
COUT
DVDD
DGND
CCLK
CLATCH
Description
Analog Ground.
Master Clock Input/ Crystal Oscillator Input.
Master Clock Output/ Crystal Oscillator Output.
Analog Ground.
Analog Power Supply. Connect to analog 3.3 V supply.
DAC 3 Left Output.
No Connect.
DAC 3 Right Output.
No Connect.
DAC 4 Left Output.
No Connect.
DAC 4 Right Output.
No Connect.
Power-Down Reset (Active Low).
DAC Input 4 (Input to DAC 4 L and R).
Digital Ground.
Digital Power Supply. Connect to digital 3.3 V supply.
DAC Input 3 (Input to DAC 3 L and R).
DAC Input 2 (Input to DAC 2 L and R).
DAC Input 1 (Input to DAC 1 L and R).
Bit Clock for DACs.
LR Clock for DACs.
+5V Input to Regulator, Emitter of Pass Transistor
+3.3V Output of Regulator, Collector of Pass Transistor
Drive for Base of Pass Transistor
ADC Serial Data Output 2 (ADC 2 L and R).
ADC Serial Data Output 1 (ADC 1 L and R).
Bit Clock for ADCs.
LR Clock for ADCs.
Control Data Input (SPI)
Control Data Output (SPI)
Digital Power Supply. Connect to digital 3.3 V supply.
Digital Ground.
Control Clock Input (SPI)
Latch Input for Control Data (SPI)
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