參數(shù)資料
型號(hào)： Eval-AD1940EB
廠商： Analog Devices, Inc.
英文描述： SigmaDSP-TM Multichannel 28-Bit Audio Processor
中文描述： SigmaDSP的，商標(biāo)多通道28位音頻處理器
文件頁(yè)數(shù)： 18/32頁(yè)
文件大?。?/td> 478K
代理商： EVAL-AD1940EB
AD1940
The four ramping curve types are
1.
Linear—Value slews to target using a fixed step size.
2.
Constant dB—Value slews to target using the current value
to calculate the step size. The resulting curve has a constant
rise and decay when measured in dB.
3.
RC-type—Value slews to target using the difference
between target and current values to calculate the step size,
producing a simple RC type curve for rising and falling.
4.
Constant Time—Value slews to the target in a fixed
number of steps in a linear fashion. The control port mute
has no affect on this type.
Rev. 0 | Page 18 of 32
Table 16 Target/Slew RAM Ramp Type Settings
Setting
00
01
10
11
Ramp Type
Linear
Constant dB
RC-Type
Constant Time
The following sections detail how the control port writes to the
target/slew RAM to control the time constant and ramp type
parameters.
Ramp Types 1–3: Linear, Constant dB, RC-type (34-Bit Write)
The target word for the first three ramp types is broken up into
three parts. The 34-bit command is written with six leading 0s
to extend the data write to five bytes. The parts of the target
RAM write are described below.
Ramp Type (2 bits)
Time Constant (4 bits)
0000 = Fastest
1111 = Slowest
Data (28 Bits): 5.23 Format
Ramp Type 4—Constant Time (34-Bit Write)
The target word for the constant time ramp type is written in
five parts, with the 34-bit command again written with six
leading zeros to extend the data write to five bytes. The parts of
the constant time target RAM write are described below.
Ramp Type (2 bits).
Update Step (1 bit). Set to 1 when new target is loaded to
trigger step value update. Value is automatically reset after
the step value is updated.
Number of Steps (3 bits). The number of steps that it takes to
slew to the target value is set by these three bits, with the
number of steps equal to 2
3-bit setting + 6
.
000 = 64
001 = 128
010 = 256
011 = 512
100 = 1024
101 = 2048
110 = 4096
111 = 8196
Data (16 bits). 2.14 format.
Reserved (12 bits). When writing to the RAM, these bits
should all be set to 0.
Target and Slew RAM Initialization
On reset, the target/slew RAM initializes to preset values. The
target RAM initializes to a linear ramp type with a time
constant of 5 and the data set to 1.0. The slew RAM initializes to
a value of 1.0. These defaults give a full-scale (1.0 to 0.0) ramp
time of 21.3 ms.
Linear Update Math
Linear math is the addition or subtraction of a constant value
(step). The equation to describe this step size is
(
)
20
10
13
5
2
2
tconst
×
=
step
The result of the equation is normalized to 5.23 data format.
This gives a time constant range from 6.75 ms to 213.4 ms.
(–60 dB relative to 0 dB full scale). An example of this kind of
update is shown in Figure 11. All slew RAM figure examples,
except the second constant time plot, show a ramp from –80 dB
to 0 dB (full scale). All figures except the constant time plots
(Figure 14 and Figure 15) use a time constant of 0x7 (0x0 being
the fastest and 0xF being the slowest).
TIME (ms)
O
1
0.4
0.6
0.8
0.2
0
–0.4
–0.2
–1
–0.8
–0.6
0
10
20
30
0
Figure 11. Slew RAM—Linear Update Plot
Constant dB and RC-type (Exponential) Update Math
Exponential math is accomplished by shifts and adds with a
range from 6.1 ms to 1.27 s (–60 dB relative to 0 dB full scale).
When the ramp type is set to 01 (constant dB), each step size is
set to the current value in the slew data. When the ramp type
bits are set to 10 (RC type), the step sizes are equal to the
difference between the values in the target RAM and slew RAM.
Figure 12 and Figure 13 show examples of this type of
target/slew RAM ramping. A decaying plot of both the
constant dB and RC-type ramps would be a mirror image of
what is shown in Figure 12.
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