參數(shù)資料
型號(hào)： Eval-AD1940EB
廠商： Analog Devices, Inc.
英文描述： SigmaDSP-TM Multichannel 28-Bit Audio Processor
中文描述： SigmaDSP的，商標(biāo)多通道28位音頻處理器
文件頁(yè)數(shù)： 25/32頁(yè)
文件大?。?/td> 478K
代理商： EVAL-AD1940EB
AD1940
Table 33. Serial Output Control Register 1
(Channels 0–7) (2644)
Register Bits
Function
15
Dither Enable
0 = Diabled
1 = Enabled
14
Internally Link TDM Streams into Single,
16-Channel Stream
0 = Indepenent
1 = Linked
13
LRCLK Polarity
0 = Frame Begins on Falling Edge
1 = Frame Begins on Rising Edge
12
BCLK Polarity
0 = Data Changes on Falling Edge
1 = Data Changes on Rising Edge
11
Master/Slave
0 = Slave
1 = Master
10:9
BCLK Frequency (Master Mode only)
00 = core_clock/24
01 = core_clock/12
10 = core_clock/6
11 = core_clock/3
8:7
Frame Sync Frequency (Master Mode only)
00 = core_clock/1536
01 = core_clock/768
10 = core_clock/384
6
Frame Sync Type
0 = LRCLK
1 = Pulse
5
Serial Output/TDM Mode Control
0 = 8 Serial Data Outputs
1 = Enable TDM (8- or 16-Channel) on
SDATA_OUT0
4:2
MSB Position
000 = Delay by 1
001 = Delay by 0
010 = Delay by 8
011 = Delay by 12
100 = Delay by 16
101 Reserved
111 Reserved
1:0
Output Word Length, Channels 0–7
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
11 = 16 Bits
Rev. 0 | Page 25 of 32
Table 34. Serial Output Control Register 2
(Channels 8–15) (2645)
Register Bits
Function
15
Dither Enable
0 = Disabled
1 = Enabled
14
Data Capture Serial Out Enable
(Uses SDATA_OUT7)
0 = Disable
1 = Enable
13
LRCLK Polarity
0 = Frame Begins on Falling Edge
1 = Frame Begins on Rising Edge
12
BCLK Polarity
0 = Data Changes on Falling Edge
1 = Data Changes on Rising Edge
11
Master/Slave
0 = Slave
1 = Master
10:9
BCLK Frequency (Master Mode only)
00 = core_clock/24
01 = core_clock/12
10 = core_clock/6
11 = core_clock/3
8:7
Frame Sync Frequency (Master Mode only)
00 = core_clock/1536
01 = core_clock/768
10 = core_clock/384
6
Frame Sync Type
0 = LRCLK
1 = Pulse
5
Serial Output/TDM Mode Control
0 = 8 Serial Data Outputs
1 = Enable TDM on SDATA_OUT4 (8-Channel)
or SDATA_OUT0 (16-Channel)
4:2
MSB Position
000 = Delay by 1
001 = Delay by 0
010 = Delay by 8
011 = Delay by 12
100 = Delay by 16
101 Reserved
111 Reserved
1:0
Output Word Length, Channels 8–15
00 = 24 Bits
01 = 20 Bits
10 = 16 Bits
11 = 16 Bits
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