- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄362799 > Eval-AD1940EB (Analog Devices, Inc.) SigmaDSP-TM Multichannel 28-Bit Audio Processor PDF資料下載
參數(shù)資料
| 型號： | Eval-AD1940EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | SigmaDSP-TM Multichannel 28-Bit Audio Processor |
| 中文描述： | SigmaDSP的，商標(biāo)多通道28位音頻處理器 |
| 文件頁數(shù)： | 27/32頁 |
| 文件大?。?/td> | 478K |
| 代理商： | EVAL-AD1940EB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當(dāng)前第27頁第28頁第29頁第30頁第31頁第32頁
AD1940
BCLK Polarity (Bit 3)
This bit controls on which edge of the bit clock the input data
changes, and on which edge it is clocked. Data changes on the
falling edge of BCLK_IN when this bit is set to 0, and on the
rising edge when this bit is set at 1.
Serial Input Mode (Bits 2:0)
These two bits control the data format that the input port
expects to receive. Bits 3 and 4 of this control register will
override the settings in Bits 2:0, so all four bits must be changed
together for proper operation in some modes. The clock
diagrams for these modes are shown in Figure 16, Figure 17,
and Figure 18. Note that for left-justified and right-justified
modes the LRCLK polarity is high, then low, which is opposite
from the default setting of Bit 4.
Rev. 0 | Page 27 of 32
When these bits are set to accept a TDM input, the AD1940’s
data starts after the edge defined by Bit 4. Figure 19 shows an
8-channel TDM stream with a high-to-low triggered LRCLK
and data changing on the falling edge of the BCLK. The
AD1940 expects the MSB of each data slot delayed by one
BCLK from the beginning of the slot, just like in the stereo I
2
S
format. In 8-channel TDM mode, Channels 0 to 3 will be in the
first half of the frame, and Channels 4 to 7 will be in the second
half. When in 16-channel TDM mode, the first half-frame will
hold Channels 0 to 7, and the second half-frame will have
Channels 8 to 15. Figure 20 shows an example of a TDM stream
running with a pulse word clock, which would be used to
interface to ADI codecs in their auxiliary mode. To work in this
mode on either the input or output serial ports, the AD1940
should be set to frame beginning on the rising edge of LRCLK,
data changing on the falling edge of BCLK, and MSB position
delayed from the start of the word clock by one BCLK.
Table 32 explains the clock settings for each of these formats.
LRCLK
BCLK
SDATA
MSB
LEFT CHANNEL
LSB
MSB
RIGHT CHANNEL
LSB
1 /F
S
0
Figure 16. I
2
S Mode—16 to 24 Bits per Channel
LRCLK
BCLK
SDATA
LEFT CHANNEL
MSB
LSB
MSB
RIGHT CHANNEL
LSB
1 /F
S
0
Figure 17. Left-Justified Mode—16 to 24 Bits per Channel
LRCLK
BCLK
SDATA
LEFT CHANNEL
MSB
LSB
MSB
RIGHT CHANNEL
LSB
1 /F
S
0
Figure 18. Right-Justified Mode—16 to 24 Bits per Channel
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EVAL-AD1953EB | 16-bit fixed point DSP with Flash |
| EVAL-AD1958EB | PLL/Multibit DAC |
| EVAL-AD1959EB | PLL/Multibit DAC |
| EVAL-AD1974EB | 4 ADC with PLL, 192 kHz, 24-Bit Codec |
| EVAl-AD1974EBZ | 4 ADC with PLL, 192 kHz, 24-Bit Codec |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EVAL-AD1940MINIB | 制造商:Analog Devices 功能描述:SIGMADSP EVAL BD - Bulk 制造商:Rochester Electronics LLC 功能描述: |
| EVAL-AD1940MINIBZ | 功能描述:BOARD EVAL AD1940 MINI SIGMADSP RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:SigmaDSP® 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| EVAL-AD1941EB | 制造商:Analog Devices 功能描述:EVAL BD SIGMADSPMULTICHANAUDIO PROCESSOR - Bulk |
| EVAL-AD1953EB | 制造商:Analog Devices 功能描述:EVAL BRD FOR 3 CH 24 BIT SIG-PROCESS DAC - Bulk 制造商:Analog Devices 功能描述:EVALUATION KIT ((NS)) |
| EVAL-AD1953EBZ | 制造商:Analog Devices 功能描述:EVAL BRD FOR 3 CH 24 BIT SIG-PROCESS DAC - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。